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asics - chip sets
(387 results)-
White Papers
FPGA Based Adaptive Neuro Fuzzy Inference Controller for Full Vehicle Nonlinear Active Suspension Systems
Oct 2010
The conventional controller like the PID controller requires an exact mathematical model of the controlled system to meet as much control objectives as possible. If it is difficult to establish...
Provided by University of Sussex
-
White Papers
Towards the Analysis of Transactional Software
Oct 2007
The computer-architecture community's recent focus on multi-core architectures has spurred renewed interest in concurrent-programming techniques and abstractions. For programmers to take advantage...
Provided by University of Wisconsin System
-
White Papers
Level Shifter Design for Low Power Applications
Oct 2010
With the growing demand of handheld devices like cellular phones, multimedia devices, personal note books etc., low power consumption has become major design consideration for VLSI circuits and...
Provided by Guru Jambheshwar University
-
White Papers
An Analytical Model to Study Optimal Area Breakdown Between Cores and Caches in a Chip Multiprocessor
Mar 2009
A key design issue for Chip MultiProcessors (CMPs) is how to exploit the finite chip area to get the best system throughput. The most dominant area-consuming components in a CMP are processor...
Provided by University of Pittsburgh
-
White Papers
An Analysis of Database System Performance on Chip Multiprocessors
Jul 2007
Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, high levels of...
Provided by Carnegie Mellon University
-
White Papers
Scheduling Threads for Constructive Cache Sharing on CMPs
Jun 2007
In Chip MultiProcessors (CMPs), limiting the number of off - chip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for constructive cache sharing, in...
Provided by Association for Computing Machinery
-
White Papers
Dynamic Thermal Management in 3D Multicore Architectures
Jan 2009
Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently...
Provided by UC Regents
-
White Papers
Temperature Management in Multiprocessor SoCs Using Online Learning
Jun 2008
In deep submicron circuits, thermal hot spots and high temperature gradients increase the cooling costs, and degrade reliability and performance. In this paper, the authors propose a low-cost...
Provided by Association for Computing Machinery
-
White Papers
An Analytical Model for the Upper Bound on Temperature Differences on a Chip
May 2008
The main contribution of this work is an analytical model for finding the upper bound on the temperature difference among various locations on the die. The proposed model can be used in many...
Provided by Association for Computing Machinery
-
White Papers
An Accurate Flip-Flop Selection Technique for Reducing Logic SER
Mar 2008
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In particular, the...
Provided by University of Wisconsin-Madison
-
White Papers
Optimized Test Scheduling With Reduced Wrapper Cell for Embedded Core Testing
Mar 2011
The increasing Design for Test (DfT) area overhead and potential performance degradation is caused due to wrapping all the embedded cores for modular System-on-Chip (SoC) testing. This paper...
Provided by JATIT
-
White Papers
BOOM: Broadcast Optimizations for On-Chip Meshes
Mar 2011
Future many-core chips will require an on-chip network that can support broadcasts and multicasts at good power-performance. A vanilla on-chip network would send multiple unicast packets for each...
Provided by Massachusetts Institute of Technology
-
White Papers
Secure FPGA Circuits Using Controlled Placement and Routing
Oct 2007
In current Field-Programmable-LoGic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an existing circuit...
Provided by Association for Computing Machinery
-
White Papers
Energy and Performance Evaluation of an FPGA-Based SoC Platform With AES and PRESENT Coprocessors
Jul 2008
Hardware implementations of block ciphers have been intensively evaluated for years. The hardware profile, including the performance, area and power of a block cipher, only considers the block...
Provided by Springer Science+Business Media
-
White Papers
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
Jan 2009
Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integrating several soft...
Provided by Springer Science+Business Media
-
White Papers
Physical Unclonable Function and True Random Number Generator : A Compact and Scalable Implementation
May 2009
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signatures and volatile...
Provided by Association for Computing Machinery
-
White Papers
Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects
Jun 2009
Hardware masking is a well-known countermeasure against Side-Channel Attacks (SCA). Like many other countermeasures, the side-channel resistance of masked circuits is susceptible to low-level...
Provided by Springer Science+Business Media
-
White Papers
Increasing the Sensitivity of On-Chip Digital Thermal Sensors With Pre-Filtering
May 2009
Thermal monitoring has been broadly used to protect high-end integrated circuits from over-heating and to identify hot-spots in complex circuits. In this paper, the authors present a method to...
Provided by Virginia Tech
-
White Papers
A Flexible Design Flow for Software IP Binding in Commodity FPGA
Aug 2009
SoftWare Intellectual Property (SWIP) is a critical component of increasingly complex FPGA based System On Chip (SOC) designs. As a result, developers want to ensure that their SWIP sources are...
Provided by Virginia Polytechnic Institute and State University
-
White Papers
Pulsed Multi-Layered Image Filtering: A VLSI Implementation
Jun 2009
Image convolution similar to the receptive fields found in mammalian visual pathways has long been used in conventional image processing in the form of Gabor masks. However, no VLSI implementation...
Provided by Dresden University of Technology
-
White Papers
An Analysis of Delay Based PUF Implementations on FPGA
Mar 2010
Physical Unclonable Functions promise cheap, efficient, and secure identification and authentication of devices. In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in...
Provided by Springer Science+Business Media
-
White Papers
Improved Ring Oscillator PUF: An FPGA-Friendly Secure Primitive
Oct 2010
In this paper, the authors analyze Ring Oscillator (RO) based Physical Unclonable Function (PUF) on FPGAs. They show that the systematic process variation adversely affects the ability of the...
Provided by International Association for Cryptologic Research
-
White Papers
A Flexible Design Flow for Software IP Binding in FPGA
Sep 2010
SoftWare Intellectual Property (SWIP) is a critical component of increasingly complex Field Programmable Gate Arrays (FPGA)-based System-On-Chip (SOC) designs. As a result, developers want to...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Polymorphic On-Chip Networks
Mar 2008
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. The authors begin this...
Provided by University of Washington
-
White Papers
Comparing Memory Systems for Chip Multiprocessors
Jun 2007
There are two basic models for the on-chip memory in CMP systems: Hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison of the two models...
Provided by Association for Computing Machinery
-
White Papers
Practical Approach to Programmable Analog Circuits With Memristors
Jan 2010
The authors suggest an approach to use memristors (resistors with memory) in programmable analog circuits. The idea consists in a circuit design in which low voltages are applied to memristors...
Provided by University of South Carolina
-
White Papers
A Method to Solve the Probe Load Effection in the High Speed Digital Circuit
Jun 2009
The measuring result has much business with the performance of the oscilloscope probe. First the authors analyze the probe load effection, and then present a method to solve the problem by using...
Provided by Tianjin Polytechnic University
-
White Papers
Schedulability Analysis for Fixed Priority Wormhole Switching in On-Chip Networks
Nov 2008
In this paper, the authors discuss a real-time on-chip communication service with a priority-based wormhole switching policy. A novel off-line schedulability analysis approach and its extension...
Provided by University of York
-
White Papers
Performance Benefits of Monolithically Stacked 3-D FPGA
Mar 2010
The performance benefits of a monolithically stacked Three-Dimensional (3-D) Field-Programmable Gate Array (FPGA), whereby the programming overhead of an FPGA is stacked on top of a standard CMOS...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Evaluating GPUs for Network Packet Signature Matching
Feb 2009
Modern network devices employ deep packet inspection to enable sophisticated services such as intrusion detection, traffic shaping, and load balancing. At the heart of such services is a signature...
Provided by University of Wisconsin
-
White Papers
DAMQ-Based Schemes for Efficiently Using the Buffer Spaces of a NoC Router
Oct 2009
In this paper the authors present high performance Dynamically Allocated Multi-Queue (DAMQ) buffer schemes for fault tolerance systems on chip applications that require an interconnection network....
Provided by Islamic Azad University
-
White Papers
The Importance of Including Dependencies in Trace Based Performance Analysis of On-Chip Networks
Dec 2009
With the advent of large scale chip-level multiprocesssors, there is renewed interest in the design and analysis of on-chip networks. The use of full system simulation is the most accurate way to...
Provided by UC Regents
-
White Papers
A Statistical Approach to Contention Modeling for High-Level Heterogeneous Multiprocessor Simulation
Jan 2011
Single chip systems featuring multiple heterogeneous processors and a variety of communication and memory architectures have emerged to satisfy the demand for networking, handheld computing, and...
Provided by Carnegie Mellon University
-
White Papers
Don't Forget Memories - A Case Study Redesigning a Pattern Counting ASIC Circuit for FPGAs
Oct 2008
Modern embedded compute platforms increasingly contain both microprocessors and Field-Programmable Gate Arrays (FPGAs). The FPGAs may implement accelerators or other circuits to speedup...
Provided by Association for Computing Machinery
-
White Papers
Practical Off-Chip Meta-Data for Temporal Memory Streaming
Dec 2008
Prior research demonstrates that temporal memory streaming and related address-correlating prefetchers improve performance of commercial server workloads through increased memory level...
Provided by University of Michigan
-
White Papers
Power-Driven Design of Router Microarchitectures in On-Chip Networks
Jan 2011
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-chip...
Provided by Princeton University
-
White Papers
Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-Nm SRAMs
Aug 2007
A mathematical Bit Error Rate (BER) model for upsets in memories protected by Error-Correcting Codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
TID Damage and Annealing Response of 90 Nm Commercial-Density SRAMs
Sep 2008
The authors characterize the TID resilience and annealing response of high-density SRAMs, fabricated in 90 nm commercial processes. Results demonstrate intrinsic SRAM hardness at 300 krad(Si), but...
Provided by University of Southern California
-
White Papers
Multicast Routing With Dynamic Packet Fragmentation
May 2009
Networks-on-Chip (NoCs) become a critical design factor as Chip MultiProcessors (CMPs) and Systems on a Chip (SoCs) scale up with technology. With fundamental benefits of high bandwidth and...
Provided by Association for Computing Machinery
-
White Papers
Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers
Mar 2009
Conventional packet-switched on-chip routers provide good resource sharing while minimizing latencies through various techniques. A Virtual Channel (VC) is allocated on a per-packet basis and held...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Implementation of Generic Algorithm Using VHDL on FPGA
Sep 2011
The development of a flexible Very-Large-Scale Integration (VLSI) for GA has been proposed in this paper. For the hardware architecture, the authors have develop on a Random Number Generator...
Provided by International Journal of Scientific & Engineering Research
-
White Papers
3-D Camera SoPC Design Architecture
Nov 2011
It is often seen that the available knowledge base within an organisation influences the selection of the design platform. The two major contenders for signal processing hardware platforms are DSP...
Provided by International Journal of Scientific & Engineering Research
-
White Papers
CORDIC Algorithm Implementation in FPGA for Computation of Sine & Cosine Signals
Dec 2011
Many hardware algorithms exist to handle the hardware intensive signal processing problems. Among these algorithms is a set of shift-add algorithms collectively known as CORDIC for computing a...
Provided by International Journal of Scientific & Engineering Research
-
White Papers
Securing Netlist-Level FPGA Design Through Exploiting Process Variation and Degradation
Feb 2011
The continuously widening gap between the Non-Recurring Engineering (NRE) and Recurring Engineering (RE) costs of producing Integrated Circuit (IC) products in the past few decades gives high...
Provided by University of California
-
White Papers
Robust Passive Hardware Metering
Sep 2011
Current hardware metering techniques, which use manifestational properties of gates for ID extraction, are weakened by the non-uniform effects of aging in conjunction with variations in...
Provided by University of California
-
White Papers
Integrated Circuit Digital Rights Management Techniques Using Physical Level Characterization
Oct 2011
Digital Rights Management (DRM) of Integrated Circuits (ICs) is a crucially important task both economically and strategically. Several IC metering techniques have been proposed, but until now...
Provided by Association for Computing Machinery
-
White Papers
Integrated Circuit Security Techniques Using Variable Supply Voltage
Jun 2011
This paper addresses Integrated Circuit (IC) security issues by using supply voltage based Gate-Level Characterization (GLC). The authors' GLC scheme is capable of characterizing both...
Provided by Association for Computing Machinery
-
White Papers
A Gate Level Sensor Network for Integrated Circuits Temperature Monitoring
Jan 2011
The authors present the first sensor network architecture to monitor Integrated Circuits (IC) thermal and energy activity. The sensor network consists of a set of simple gates, which are...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Leakage Minimization Using Self Sensing and Thermal Management
Aug 2010
The authors have developed a system architecture, measuring and modeling techniques, and algorithms for on-line power and energy optimization and thermal management. The starting point for their...
Provided by Association for Computing Machinery
-
White Papers
Trusted Integrated Circuits: A Nondestructive Hidden Characteristics Extraction Approach
Oct 2008
The authors have developed a methodology for unique identification of Integrated Circuits (ICs) that addresses untrusted fabrication and other security problems. The new method leverages...
Provided by Springer Science+Business Media
-
White Papers
Input Vector Control for Post-Silicon Leakage Current Minimization in the Presence of Manufacturing Variability
Jun 2008
The authors present the first approach for post-silicon leakage power reduction through Input Vector Control (IVC) that takes into account the impact of the Manufacturing Variability (MV). Because...
Provided by Institute of Electrical and Electronics Engineers
-
Whitepapers - Video
Securing the Cloud with Intel Trusted Execution Technology Usage Models
Jun 2011
Intel's Sr. Security Engineer, James Greene talks about usage models around trusted compute pools, secure on-boarding of virtual machines to a cloud environment and auditing of the security...
Provided by Intel Corporation
-
White Papers
Ant Colony Based Approach for Solving FPGA Routing
Jul 2011
This paper is based on an ant colony optimization algorithm (ASDR) for solving FPGA routing for a route based routing constraint model in FPGA design architecture. In this approach FPGA routing...
Provided by International Journal of Computer Science Issues
-
White Papers
Designing a WISHBONE Protocol Network Adapter for an Asynchronous Network-on-Chip
Jul 2011
The Scaling of microchip technologies, from micron to sub-micron and now to Deep Sub-Micron (DSM) range, has enabled large scale Systems-on-Chip (SoC). In future Deep Sub-Micron (DSM) designs, the...
Provided by International Journal of Computer Science Issues
-
Whitepapers
Intel IT Executive Insights: Intel IT's Cloud Computing Strategy
Jan 2012
Cloud computing is only growing and innovating and at Intel, it's one of their top 3 IT objectives for 2012. The idea of a virtualized data center is changing the way Intel looks at its...
Provided by Intel Corporation
-
Whitepapers
Inside Intel IT on Cloud Computing and Security
Jan 2012
Certainly no one expects that a company like Intel doesn't have issues when it comes to computing in the cloud, they do by the way. The real question is, how do they handle them, what are Intel...
Provided by Intel Corporation
-
Whitepapers
Intel brings new experiences to life via Cloud Computing
Dec 2011
It seems that today's cloud technology is constantly pushing the envelope of what is or isn't possible in computing. Something as simple as putting a few letters into a search engine and getting...
Provided by Intel Corporation
-
White Papers
A 5.7Gbps Row-Based Layered Scheduling LDPC Decoder for IEEE 802.15.3c Applications
Nov 2010
A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A 90 nm All-digital Smart Temperature Sensor With Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications
Jan 2010
This paper provides an all-digital smart temperature sensor with dual-mode transceiver chipset for Wireless Body Area Network (WBAN). The measurement results show that the proposed temperature...
Provided by Springer Science+Business Media
-
White Papers
On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays
Jan 2008
The authors investigate the power and energy implications of using embedded FPGA memory blocks to implement logic. Previous studies have shown that this technique provides extremely dense...
Provided by Hindawi Publishing
-
White Papers
Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology
Sep 2008
In current reconfigurable architectures, the interconnection structures increasingly contribute more to the delay and power consumption. The demand for increased clock frequencies and logic...
Provided by Hindawi Publishing
-
White Papers
Burst-Mode Asynchronous Controllers on FPGA
Oct 2008
FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. The authors propose a method...
Provided by Hindawi Publishing
-
White Papers
Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration
Nov 2008
In real-time signal processing, a single application often has multiple computationally intensive kernels that can benefit from acceleration using custom or reconfigurable hardware platforms, such...
Provided by Hindawi Publishing
-
White Papers
The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units
Oct 2008
This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and...
Provided by Hindawi Publishing
-
White Papers
Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs
Jan 2009
Modern FPGAs contain embedded DSP blocks, which can be configured as multipliers with more than one possible size. FPGA-based designs using these multigranular embedded blocks become more...
Provided by Hindawi Publishing
-
White Papers
High level modeling of Dynamic Reconfigurable FPGAs
Mar 2009
As System-on-Chip (SoC) based embedded systems have become a defacto industry standard, their overall design complexity has increased exponentially in recent years, necessitating the introduction...
Provided by Hindawi Publishing
-
White Papers
A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks
Apr 2009
FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs) applications, offering the key requirement of reconfigurability. However,...
Provided by Hindawi Publishing
-
White Papers
Multilevel Simulation of Heterogeneous Reconfigurable Platforms
Apr 2009
This paper presents a general system-level simulation and testing methodology for reconfigurable System-on-Chips, starting from behavioral specifications of system activities to multilevel...
Provided by Hindawi Publishing
-
White Papers
A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime
May 2009
Run-time reconfigurable system-on-chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying...
Provided by Hindawi Publishing
-
White Papers
An Adaptive Message Passing MPSoC Framework
Apr 2009
Multi-Processor Systems-on-Chips (MPSoCs) offer superior performance while maintaining flexibility and reusability thanks to software oriented personalization. While most MPSoCs are today...
Provided by Hindawi Publishing
-
White Papers
A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation
May 2009
Channel estimation in wireless communication systems is usually accomplished by inserting, along with the information, a series of known symbols, whose analysis is used to define the parameters of...
Provided by Hindawi Publishing
-
White Papers
A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips
May 2009
The authors present a heuristic algorithm for the run-time distribution of task sets in a homogeneous Multiprocessor network-on-chip. The algorithm is itself distributed over the processors and...
Provided by Hindawi Publishing
-
White Papers
Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings
Jun 2009
A True Random Number Generator (TRNG) is an important component in cryptographic systems. Designing a fast and secure TRNG in an FPGA is a challenging task. In this paper, the authors analyze the...
Provided by Hindawi Publishing
-
White Papers
FPGA Interconnect Topologies Exploration
Jul 2009
This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest...
Provided by Hindawi Publishing
-
White Papers
A Hardware Filesystem Implementation with Multidisk Support
Aug 2009
Modern High-End Computing systems frequently include FPGAs as compute accelerators. These programmable logic devices now support disk controller IP cores which offer the ability to introduce new,...
Provided by Hindawi Publishing
-
White Papers
An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures
Sep 2009
This paper proposes an exact ILP formulation for the task scheduling problem on a 2D dynamically and partially reconfigurable architecture. The authors' approach takes physical constraints of the...
Provided by Hindawi Publishing
-
White Papers
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms
Dec 2009
This paper presents the OveRSoC project. The objective is to develop an exploration and validation methodology of embedded Real Time Operating Systems (RTOSs) for Reconfigurable...
Provided by Hindawi Publishing
-
White Papers
Power Characterisation for Fine-Grain Reconfigurable Fabrics
Oct 2009
This paper proposes a benchmarking methodology for characterising the power consumption of the fine-grain fabric in reconfigurable architectures. This methodology is part of the GroundHog 2009...
Provided by Hindawi Publishing
-
White Papers
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures
Nov 2009
The dynamic and partial reconfiguration of FPGAs enables the dynamic placement in reconfigurable zones of the tasks that describe an application. However, the dynamic management of the tasks...
Provided by Hindawi Publishing
-
White Papers
Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs
Jan 2010
The authors present a method for implementing high speed Finite Impulse Response (FIR) filters on Field Programmable Gate Arrays (FPGAs). Their algorithm is a multiplierless technique where fixed...
Provided by Hindawi Publishing
-
White Papers
Towards the Analysis of Transactional Software
Oct 2007
The computer-architecture community's recent focus on multi-core architectures has spurred renewed interest in concurrent-programming techniques and abstractions. For programmers to take advantage...
Provided by University of Wisconsin System
-
White Papers
Level Shifter Design for Low Power Applications
Oct 2010
With the growing demand of handheld devices like cellular phones, multimedia devices, personal note books etc., low power consumption has become major design consideration for VLSI circuits and...
Provided by Guru Jambheshwar University
-
White Papers
An Analytical Model to Study Optimal Area Breakdown Between Cores and Caches in a Chip Multiprocessor
Mar 2009
A key design issue for Chip MultiProcessors (CMPs) is how to exploit the finite chip area to get the best system throughput. The most dominant area-consuming components in a CMP are processor...
Provided by University of Pittsburgh
-
White Papers
An Analysis of Database System Performance on Chip Multiprocessors
Jul 2007
Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, high levels of...
Provided by Carnegie Mellon University
-
White Papers
Scheduling Threads for Constructive Cache Sharing on CMPs
Jun 2007
In Chip MultiProcessors (CMPs), limiting the number of off - chip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for constructive cache sharing, in...
Provided by Association for Computing Machinery
-
White Papers
Dynamic Thermal Management in 3D Multicore Architectures
Jan 2009
Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently...
Provided by UC Regents
-
White Papers
Temperature Management in Multiprocessor SoCs Using Online Learning
Jun 2008
In deep submicron circuits, thermal hot spots and high temperature gradients increase the cooling costs, and degrade reliability and performance. In this paper, the authors propose a low-cost...
Provided by Association for Computing Machinery
-
White Papers
An Analytical Model for the Upper Bound on Temperature Differences on a Chip
May 2008
The main contribution of this work is an analytical model for finding the upper bound on the temperature difference among various locations on the die. The proposed model can be used in many...
Provided by Association for Computing Machinery
-
White Papers
An Accurate Flip-Flop Selection Technique for Reducing Logic SER
Mar 2008
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In particular, the...
Provided by University of Wisconsin-Madison
-
White Papers
Optimized Test Scheduling With Reduced Wrapper Cell for Embedded Core Testing
Mar 2011
The increasing Design for Test (DfT) area overhead and potential performance degradation is caused due to wrapping all the embedded cores for modular System-on-Chip (SoC) testing. This paper...
Provided by JATIT
-
White Papers
BOOM: Broadcast Optimizations for On-Chip Meshes
Mar 2011
Future many-core chips will require an on-chip network that can support broadcasts and multicasts at good power-performance. A vanilla on-chip network would send multiple unicast packets for each...
Provided by Massachusetts Institute of Technology
-
White Papers
Secure FPGA Circuits Using Controlled Placement and Routing
Oct 2007
In current Field-Programmable-LoGic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an existing circuit...
Provided by Association for Computing Machinery
-
White Papers
Energy and Performance Evaluation of an FPGA-Based SoC Platform With AES and PRESENT Coprocessors
Jul 2008
Hardware implementations of block ciphers have been intensively evaluated for years. The hardware profile, including the performance, area and power of a block cipher, only considers the block...
Provided by Springer Science+Business Media
-
White Papers
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
Jan 2009
Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integrating several soft...
Provided by Springer Science+Business Media
-
White Papers
Physical Unclonable Function and True Random Number Generator : A Compact and Scalable Implementation
May 2009
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signatures and volatile...
Provided by Association for Computing Machinery
-
White Papers
Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects
Jun 2009
Hardware masking is a well-known countermeasure against Side-Channel Attacks (SCA). Like many other countermeasures, the side-channel resistance of masked circuits is susceptible to low-level...
Provided by Springer Science+Business Media
-
White Papers
Increasing the Sensitivity of On-Chip Digital Thermal Sensors With Pre-Filtering
May 2009
Thermal monitoring has been broadly used to protect high-end integrated circuits from over-heating and to identify hot-spots in complex circuits. In this paper, the authors present a method to...
Provided by Virginia Tech
-
White Papers
A Flexible Design Flow for Software IP Binding in Commodity FPGA
Aug 2009
SoftWare Intellectual Property (SWIP) is a critical component of increasingly complex FPGA based System On Chip (SOC) designs. As a result, developers want to ensure that their SWIP sources are...
Provided by Virginia Polytechnic Institute and State University
-
White Papers
Pulsed Multi-Layered Image Filtering: A VLSI Implementation
Jun 2009
Image convolution similar to the receptive fields found in mammalian visual pathways has long been used in conventional image processing in the form of Gabor masks. However, no VLSI implementation...
Provided by Dresden University of Technology
-
White Papers
An Analysis of Delay Based PUF Implementations on FPGA
Mar 2010
Physical Unclonable Functions promise cheap, efficient, and secure identification and authentication of devices. In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in...
Provided by Springer Science+Business Media
-
White Papers
Improved Ring Oscillator PUF: An FPGA-Friendly Secure Primitive
Oct 2010
In this paper, the authors analyze Ring Oscillator (RO) based Physical Unclonable Function (PUF) on FPGAs. They show that the systematic process variation adversely affects the ability of the...
Provided by International Association for Cryptologic Research
-
White Papers
A Flexible Design Flow for Software IP Binding in FPGA
Sep 2010
SoftWare Intellectual Property (SWIP) is a critical component of increasingly complex Field Programmable Gate Arrays (FPGA)-based System-On-Chip (SOC) designs. As a result, developers want to...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Polymorphic On-Chip Networks
Mar 2008
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. The authors begin this...
Provided by University of Washington
-
White Papers
Comparing Memory Systems for Chip Multiprocessors
Jun 2007
There are two basic models for the on-chip memory in CMP systems: Hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison of the two models...
Provided by Association for Computing Machinery
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White Papers
Practical Approach to Programmable Analog Circuits With Memristors
Jan 2010
The authors suggest an approach to use memristors (resistors with memory) in programmable analog circuits. The idea consists in a circuit design in which low voltages are applied to memristors...
Provided by University of South Carolina
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White Papers
A Method to Solve the Probe Load Effection in the High Speed Digital Circuit
Jun 2009
The measuring result has much business with the performance of the oscilloscope probe. First the authors analyze the probe load effection, and then present a method to solve the problem by using...
Provided by Tianjin Polytechnic University
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White Papers
Schedulability Analysis for Fixed Priority Wormhole Switching in On-Chip Networks
Nov 2008
In this paper, the authors discuss a real-time on-chip communication service with a priority-based wormhole switching policy. A novel off-line schedulability analysis approach and its extension...
Provided by University of York
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White Papers
Performance Benefits of Monolithically Stacked 3-D FPGA
Mar 2010
The performance benefits of a monolithically stacked Three-Dimensional (3-D) Field-Programmable Gate Array (FPGA), whereby the programming overhead of an FPGA is stacked on top of a standard CMOS...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Evaluating GPUs for Network Packet Signature Matching
Feb 2009
Modern network devices employ deep packet inspection to enable sophisticated services such as intrusion detection, traffic shaping, and load balancing. At the heart of such services is a signature...
Provided by University of Wisconsin
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White Papers
DAMQ-Based Schemes for Efficiently Using the Buffer Spaces of a NoC Router
Oct 2009
In this paper the authors present high performance Dynamically Allocated Multi-Queue (DAMQ) buffer schemes for fault tolerance systems on chip applications that require an interconnection network....
Provided by Islamic Azad University
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White Papers
The Importance of Including Dependencies in Trace Based Performance Analysis of On-Chip Networks
Dec 2009
With the advent of large scale chip-level multiprocesssors, there is renewed interest in the design and analysis of on-chip networks. The use of full system simulation is the most accurate way to...
Provided by UC Regents
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White Papers
A Statistical Approach to Contention Modeling for High-Level Heterogeneous Multiprocessor Simulation
Jan 2011
Single chip systems featuring multiple heterogeneous processors and a variety of communication and memory architectures have emerged to satisfy the demand for networking, handheld computing, and...
Provided by Carnegie Mellon University
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White Papers
Don't Forget Memories - A Case Study Redesigning a Pattern Counting ASIC Circuit for FPGAs
Oct 2008
Modern embedded compute platforms increasingly contain both microprocessors and Field-Programmable Gate Arrays (FPGAs). The FPGAs may implement accelerators or other circuits to speedup...
Provided by Association for Computing Machinery
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White Papers
Practical Off-Chip Meta-Data for Temporal Memory Streaming
Dec 2008
Prior research demonstrates that temporal memory streaming and related address-correlating prefetchers improve performance of commercial server workloads through increased memory level...
Provided by University of Michigan
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White Papers
Power-Driven Design of Router Microarchitectures in On-Chip Networks
Jan 2011
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-chip...
Provided by Princeton University
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White Papers
Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-Nm SRAMs
Aug 2007
A mathematical Bit Error Rate (BER) model for upsets in memories protected by Error-Correcting Codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
TID Damage and Annealing Response of 90 Nm Commercial-Density SRAMs
Sep 2008
The authors characterize the TID resilience and annealing response of high-density SRAMs, fabricated in 90 nm commercial processes. Results demonstrate intrinsic SRAM hardness at 300 krad(Si), but...
Provided by University of Southern California
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White Papers
Multicast Routing With Dynamic Packet Fragmentation
May 2009
Networks-on-Chip (NoCs) become a critical design factor as Chip MultiProcessors (CMPs) and Systems on a Chip (SoCs) scale up with technology. With fundamental benefits of high bandwidth and...
Provided by Association for Computing Machinery
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White Papers
Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers
Mar 2009
Conventional packet-switched on-chip routers provide good resource sharing while minimizing latencies through various techniques. A Virtual Channel (VC) is allocated on a per-packet basis and held...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Development Strategy of Next Generation Singlechip Smart Inverters for Motor Control Applications
Jul 2007
In smart-power IC technologies the trend toward more functional integration is expected to intensify further, producing more compact, efficient, and user-friendly power modules. It looks that in...
Provided by Technical University of Cluj-Napoca
