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asics - chip sets
(387 results)-
White Papers
Development Strategy of Next Generation Singlechip Smart Inverters for Motor Control Applications
Jul 2007
In smart-power IC technologies the trend toward more functional integration is expected to intensify further, producing more compact, efficient, and user-friendly power modules. It looks that in...
Provided by Technical University of Cluj-Napoca
-
White Papers
MIRA: A Multi-Layered On-Chip Interconnect Router Architecture
Apr 2008
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology. However,...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Performance Analysis of Software to Hardware Task Migration in Codesign
Jan 2010
The complexity of multimedia applications in terms of intensity of computation and heterogeneity of treated data led the designers to embark them on multiprocessor systems on chip. The complexity...
Provided by International Journal of Computer Science Issues
-
White Papers
Bilateral Testing of Nano-Scale Fault-Tolerant Circuits
Jan 2009
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. Because...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
High Speed 1-Bit Bypass Adder Design for Low Precision Additions
Jul 2007
In this paper, the authors propose a high speed adder which is adopted for the reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture adopts...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
FleXilicon Architecture and Its VLSI Implementation
Aug 2009
In this paper, the authors present a new coarse-grained reconfigurable architecture called FleXilicon for multimedia and wireless communications, which improves resource utilization and achieves a...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
High Speed Channel Coding Architectures for the Uncoordinated or Channel
Jan 2011
Though it promises high bandwidths, the optical medium is not popular in local area networks. This is because current optical networks do not offer the ease of use and setup that an uncoordinated...
Provided by UC Regents
-
White Papers
Design and Performance Analysis of Efficient Bus Arbitration Schemes for On-Chip Shared Bus Multi-Processor SoC
Sep 2008
In the resource sharing mechanism of multi-processor SoC, the on-chip communication architecture plays an important role and directly affects the performance of SoC. The traditional shared bus...
Provided by G.H. Raisoni College of Engineering
-
White Papers
Using Multiple Compacted Responses to Diagnose Scan Response Errors During Testing
Jan 2011
Scan test vector and response volume are becoming problematic, and in industrial designs are complicated by the presence of unknown values in test responses. Recent work has addressed this problem...
Provided by University of Illinois
-
White Papers
Perfect Difference Network for Network-on-Chip Architecture
Dec 2009
Network-on-Chip (NoC) is a new paradigm for designing core based System-on-Chip. Network-on-Chip has been proposed as a solution for addressing the design challenges of future high performance...
Provided by Bapurao Deshmukh College of Engineering
-
White Papers
Optimal Runtime Reconfiguration Strategies for Systolic Arrays
Oct 2009
Many computation kernels that analyze large data streams can be accelerated by converting their recurrences to parallel systolic arrays. Application domains such as bioinformatics seek to minimize...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Efficient Runtime Performance Monitoring of FPGA-based Applications
May 2009
Embedded computing platforms have long incorporated non-traditional architectures (e.g., FPGAs, ASICs) to combat the diminishing returns of Moore's Law as applied to traditional processors. These...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Determining Covers in Combinational Circuits
May 2011
In this paper the authors propose a procedure for determining 0 - or 1 - cover of an arbitrary line in a combinational circuit. When determining a cover they do not need Boolean expression for the...
Provided by International Journal of Computer Science Issues
-
White Papers
Layered Switching for Networks on Chip
Jun 2007
The authors present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To show the...
Provided by Association for Computing Machinery
-
White Papers
FPGA-Based Particle Recognition in the HADES Experiment
Nov 2010
Modern FPGA technologies are often employed in nuclear and particle physics experimental facilities to accelerate application-specific computation. The authors present the particle recognition...
Provided by KTH
-
White Papers
Network Calculus Applied to Verification of Memory Access Performance in SoCs
Aug 2007
SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes the performance of...
Provided by KTH - Royal Institute of Technology
-
White Papers
Slot Allocation Using Logical Networks for TDM Virtual-Circuit Configuration for Network-on-Chip
Aug 2007
Configuring Time-Division-Multiplexing (TDM) Virtual Circuits (VCs) for network-on-chip must guarantee conflict freedom for overlapping VCs besides allocating sufficient time slots to them. These...
Provided by KTH - Royal Institute of Technology
-
White Papers
Hardware/Software Co-Design of a General-Purpose Computation Platform in Particle Physics
Oct 2007
In this paper the authors present a hardware/software co-design based computation platform for online data processing in particle physical experiments. Their goal is to ease and accelerate the...
Provided by Giessen University
-
White Papers
FPGA-Based Adaptive Computing for Correlated Multi-Stream Processing
Dec 2009
In conventional static implementations for correlated streaming applications, computing resources may be inefficiently utilized since multiple stream processors may supply their sub-results at...
Provided by KTH Royal Institute of Technology
-
White Papers
Development and Evaluation of a Memory Consistency and Cache Coherence Protocol for the Nocsim NoC Simulator
Feb 2008
Networks on Chip (NoC) have started to replace conventional buses, especially in systems on chip and distributed systems. In a typical system with a bus, cache coherency and memory consistency...
Provided by KTH - Royal Institute of Technology
-
White Papers
Inter-Process Communication Using Pipes in FPGA-Based Adaptive Computing
Apr 2010
In FPGA-based adaptive computing, Inter-Process Communications (IPC) are required to exchange information among hardware processes which time-multiplex the resources in a same reconfigurable...
Provided by KTH Royal Institute of Technology
-
White Papers
Towards Open Network-on-Chip Benchmarks
Mar 2009
Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challenge which has...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Comparative Analysis of Transient-Fault Tolerant Schemes for Network on Chips
Jun 2009
Network on a Chip (NoC) has been proposed as a viable solution to counter the inefficiency of buses in the current VLSI on-chip interconnects. However, as the silicon chip accommodates more...
Provided by Institute of Management Sciences
-
White Papers
SML-Sys: A Functional Framework With Multiple Models of Computation for Modeling Heterogeneous System
Feb 2008
System-on-Chip and other complex distributed hardware/software systems contain heterogeneous components. High-level modeling of such systems require frameworks that provide designers with the...
Provided by KTH - Royal Institute of Technology
-
White Papers
Cluster-Based Simulated Annealing for Mapping Cores Onto 2D Mesh Networks on Chip
Mar 2008
In Network-on-Chip (NoC) application design, core-to-node mapping is an important but intractable optimization problem. In the paper, the authors use simulated annealing to tackle the mapping...
Provided by KTH Royal Institute of Technology
-
White Papers
System-on-an-FPGA Design for Real-Time Particle Track Recognition and Reconstruction in Physics Experiments
Jun 2008
In particle physics experiments, the momenta of charged particles are studied by observing their deflection in a magnetic field. Dedicated detectors measure the particle tracks and complex...
Provided by KTH - Royal Institute of Technology
-
White Papers
Energy Efficient Streaming Applications With Guaranteed Throughput on MPSoCs
Oct 2008
In this paper the authors present a design space exploration flow to achieve energy efficiency for streaming applications on MPSoCs while meeting the specified throughput constraints. The public...
Provided by Association for Computing Machinery
-
White Papers
Atca-Based Computation Platform for Data Acquisition and Triggering in Particle Physics Experiments
Jun 2008
ATCA-based computation platform for data acquisition and trigger applications in nuclear and particle physics experiments has been developed. Each Compute Node (CN) which appears as a Field...
Provided by KTH - Royal Institute of Technology
-
White Papers
Implementation of a DLI-Guard Using the AMBA AXI Protocol for Network-on-Chip
Dec 2008
Nowdays, the integration of several system components or IP blocks, such as processors, DSP units and memories on one chip is overwhelming the industry. The method of integrating several...
Provided by KTH - Royal Institute of Technology
-
White Papers
Generalization of Slot Table Size for Virtual Circuits on Nostrum Networks on Chip
Jun 2008
Since the late 1990's, the trend of integrated circuit design has been integrating several system components or IP blocks, such as processors and memories, on one chip. This is referred to the...
Provided by KTH - Royal Institute of Technology
-
White Papers
Design Space Exploration of Field Programmable Counter Arrays and Their Integration With FPGAs
Jul 2008
Field Programmable Counter Arrays (FPCAs) have been recently introduced to close the gap between FPGA and ASICs for arithmetic dominated applications. FPCAs are reconfigurable lattices that can be...
Provided by KTH - Royal Institute of Technology
-
White Papers
TDM Virtual-Circuit Configuration for Network-on-Chip
Oct 2007
In Network-on-Chip (NoC), Time-Division-Multiplexing (TDM) Virtual Circuits (VCs) have been proposed to satisfy the Quality-of-Service requirements of applications. TDM VC is a connection-oriented...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Reducing FPGA Reconfiguration Time Overhead Using Virtual Configurations
Apr 2010
Reconfiguration time overhead is a critical factor in determining the system performance of FPGA dynamically reconfigurable designs. To reduce the reconfiguration overhead, the most...
Provided by KTH Royal Institute of Technology
-
Webcasts
ProcessorPM Power Management Video
Jan 2011
Take the first step to integrate multiple processor power management devices and improve system reliability by watching this 5 minutes webcast. ProcessorPM devices are the perfect companion for...
Provided by Lattice Semiconductor
-
Webcasts
Growing Lasers on Computer Chips
Feb 2011
The first time, researchers have grown lasers from high-performance materials directly on silicon. Bringing together electrical and optical components on computer chips would speed data transfer...
Provided by MIT
-
White Papers
A Fast FPGA Implementation of Tate Pairing in Cryptography Over Binary Field
May 2008
Identity based cryptography schemes have opened a new territory for public key cryptography. Using identity based cryptography schemes, a sender can derive the public key of a receiver without...
Provided by University of Central Florida
-
White Papers
A Formal Semantics for Control and Data Flow in the Gannet Service-Based System-on-Chip Architecture
May 2008
There is a growing demand for solutions which allow the design of large and complex reconfigurable Systems-on-Chip (SoC) at high abstraction levels. The Gannet project proposes a functional...
Provided by University of Glasgow
-
White Papers
Qnet: A Modular Architecture for Reconfigurable Computing
May 2008
A packet-switched network architecture named Qnet and programming interface is presented that simplifies the integration of reconfigurable computing modules within a Field Programmable Gate Array...
Provided by Brigham Young University
-
White Papers
A Comparison of Traditional On-Chip Interconnects With Network-on-Chip Architecture
May 2008
The authors have investigated the Network-on-Chip (NOC) as an emerging on-chip interconnects technology, to understand and compare its impact on global communication delays, and power consumption...
Provided by California State University
-
White Papers
Optimal Dynamic Routing and Flow Control in Interconnection Networks on Chip
May 2008
There has been a lot of work done on NoCs to reduce latency, power consumption and congestion control. In this paper the authors have proposed a dynamic routing algorithm with a conducive flow...
Provided by Jaypee University of Information Technology
-
White Papers
Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study
Feb 2010
Reconfigurable Computers (RCs) are traditional computers extended with co-processors based on reconfigurable hardware like FPGAs. Representative RC systems include SGI RC100, SRC-6, and Cray XD1....
Provided by Hindawi Publishing
-
White Papers
New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA
Apr 2010
Currently, reconfigurable hardware devices feature a high density of heterogeneous resources to enable multitasking and offer flexibility in application needs. These concepts raise the need for...
Provided by Hindawi Publishing
-
White Papers
Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing
Jun 2010
This paper presents the design of a reconfigurable asynchronous computing element, called the Pulsed Quad-cell (PQ-cell), for constructing conformal computers. Conformal computers are systems with...
Provided by Hindawi Publishing
-
White Papers
3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans
Aug 2010
The authors propose new 3D 2-layer and 3-layer NoC architectures that utilize homogeneous regular mesh networks on a separate layer and one or two heterogeneous floorplanning layers. These...
Provided by Hindawi Publishing
-
White Papers
Mechanism of Resource Virtualization in RCS for Multitask Stream Applications
Sep 2010
Virtualization of logic, routing, and communication resources in recent FPGA devices can provide a dramatic improvement in cost-efficiency for Reconfigurable Computing systems (RCSs). The...
Provided by Hindawi Publishing
-
White Papers
Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics
Oct 2010
FPGA design of side-channel analysis countermeasures using unmasked dual-rail with pre-charge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful...
Provided by Hindawi Publishing
-
White Papers
Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic
Nov 2010
Dynamic Partial Reconfiguration (DPR) allows one to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, the authors present two new DPR...
Provided by Hindawi Publishing
-
White Papers
Reconfigurable Multiprocessor Systems: A Review
Oct 2010
Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them. This approach provides better results in terms of area, speed, and...
Provided by Hindawi Publishing
-
White Papers
Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures
Dec 2010
Field-Programmable Gate Arrays (FPGAs) and other Reconfigurable Computing (RC) devices have been widely shown to have numerous advantages including order of magnitude performance and power...
Provided by Hindawi Publishing
-
White Papers
Low-Complexity Online Synthesis for AMIDAR Processors
Dec 2010
Future chip technologies will change the way the authors deal with hardware design. First of all, logic resources will be available in vast amount. Furthermore, engineering specialized designs for...
Provided by Hindawi Publishing
-
White Papers
FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition
Sep 2010
A scalable large vocabulary, speaker independent speech recognition system is being developed using Hidden Markov Models (HMMs) for acoustic modeling and a Weighted Finite State Transducer (WFST)...
Provided by Hindawi Publishing
-
White Papers
A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos
Oct 2010
This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation that targets high-definition videos. This design can process very high-definition videos...
Provided by Hindawi Publishing
-
White Papers
An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms
Nov 2010
The design of complex circuits as SoCs presents two great challenges to designers. One is the speeding up of system functionality modeling and the second is the implementation of the system in an...
Provided by Hindawi Publishing
-
White Papers
FPGA Implementation for GMM-Based Speaker Identification
Nov 2010
In today's society, highly accurate personal identification systems are required. Passwords or pin numbers can be forgotten or forged and are no longer considered to offer a high level of...
Provided by Hindawi Publishing
-
White Papers
High-Level Synthesis of In-Circuit Assertions for Verification
Dec 2010
Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-Level Synthesis (HLS) tools have...
Provided by Hindawi Publishing
-
White Papers
Floorplacement for Partial Reconfigurable FPGA-Based Systems
Dec 2010
The authors presented a resource- and configuration-aware floor-placement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength. Their work...
Provided by Hindawi Publishing
-
White Papers
Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates
Dec 2010
The aggressive scaling of CMOS technology has increased the density and allowed the integration of multiple processors into a single chip. Although solutions based on MPSoC architectures can...
Provided by Hindawi Publishing
-
White Papers
An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads
Dec 2010
Parallel graph-oriented applications expressed in the Bulk-Synchronous Parallel (BSP) and Token Dataflow compute models generate highly-structured communication workloads from messages propagating...
Provided by Hindawi Publishing
-
White Papers
The Potential for a GPU-Like Overlay Architecture for FPGAs
Dec 2010
The authors propose a soft processor programming model and architecture inspired by Graphics Processing Units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and...
Provided by Hindawi Publishing
-
White Papers
An FPGA-Based Adaptable 200 MHz Bandwidth Channel Sounder for Wireless Communication Channel Characterisation
Jan 2011
This paper describes the development of a fast adaptable FPGA-based wide-band channel sounder with signal bandwidths of up to 200MHz and channel sampling rates up to 5.4 kHz. The application of...
Provided by Hindawi Publishing
-
White Papers
On Self-Timed Circuits in Real-Time Systems
Jan 2011
While asynchronous logic has many potential advantages compared to traditional synchronous designs, one of the major drawbacks is its unpredictability with respect to temporal behavior. Having no...
Provided by Hindawi Publishing
-
White Papers
A Vector-Like Reconfigurable Floating-Point Unit for the Logarithm
Jan 2011
The use of reconfigurable computing for accelerating floating-point intensive codes is becoming common due to the availability of DSPs in new-generation FPGAs. The authors present the design of an...
Provided by Hindawi Publishing
-
White Papers
A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs
Jan 2011
In FPGA embedded systems, designers usually have to make a compromise between numerical precision and logical resources. Scientific computations in particular, usually require highly accurate...
Provided by Hindawi Publishing
-
White Papers
Experiment Centric Teaching for Reconfigurable Processors
Dec 2010
This paper presents a setup for teaching configware to master students. The authors' approach focuses on experiment and leaning-by-doing while being supported by research activity. The central...
Provided by Hindawi Publishing
-
White Papers
Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems
Feb 2011
The design space of FPGA-based processor systems is huge, because many parameters can be modified at design- and run-time to achieve an efficient system solution in terms of performance, power and...
Provided by Hindawi Publishing
-
White Papers
Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing
Sep 2009
Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays. With...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
May 2011
Pre-bond testing of 3-D stacked Integrated Circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability because manufacturers...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Split and Merge Functions for Supporting Multiple Processing Pipelines in Mercury BLASTN
May 2010
Biosequence similarity search is an important application in computational biology. Mercury BLASTN, an FPGA-based implementation of BLAST for DNA, is one of the alternatives for fast DNA sequence...
Provided by University of Washington
-
White Papers
Mercury BLASTN Biosequence Similarity Search System: Technical Reference Guide
May 2011
The Mercury BLASTN application is a hybrid hardware-software implementation of DNA-to-DNA sequence comparison. It presents an interface similar to that of NCBI BLASTN 2.2 (and indeed uses much of...
Provided by University of Washington
-
White Papers
Design and Application of IP Core in SoC Technology
Apr 2010
SoC (System on Chip) design is a new development of design technology under the design of dedicated chip ASICs (Application Specific Integrated Circuits). It is an integrated chip design method...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Physical Synthesis With Clock-Network Optimization for Large Systems on Chips
Aug 2011
In this paper, the authors address a known hard problem - closing the gap between custom and semicustom VLSI design styles and the ASIC VLSI design style - critical to the effective design of...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits
Feb 2011
This paper presents an in-depth study of Mesh-of-Tree (MoT) topology and its application in Network-on-Chip (NoC) design for both 2-D and 3-D ICs. The performance and cost of the MoT network have...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
New Approach for Inter Networks - On - Chip Communication in Networks - In - Package
May 2008
Networks-in-Package (NiP) is a solution for inter Networks-on-Chip (NoC) communication, where power dissipation, performance, and size of processing package are the major factors. NiP is a group...
Provided by Jaypee University of Information Technology
-
White Papers
Optimal Dynamic Routing and Flow Control in Interconnection Networks on Chip
May 2008
There has been a lot of work done on NoCs to reduce latency, power consumption and congestion control. In this paper the authors have proposed a dynamic routing algorithm with a conducive flow...
Provided by Jaypee University of Information Technology
-
White Papers
A Comparison of Traditional On-Chip Interconnects With Network-on-Chip Architecture
May 2008
The authors have investigated the Network-on-Chip (NOC) as an emerging on-chip interconnects technology, to understand and compare its impact on global communication delays, and power consumption...
Provided by California State University
-
White Papers
Qnet: A Modular Architecture for Reconfigurable Computing
May 2008
A packet-switched network architecture named Qnet and programming interface is presented that simplifies the integration of reconfigurable computing modules within a Field Programmable Gate Array...
Provided by Brigham Young University
-
White Papers
A Formal Semantics for Control and Data Flow in the Gannet Service-Based System-on-Chip Architecture
May 2008
There is a growing demand for solutions which allow the design of large and complex reconfigurable Systems-on-Chip (SoC) at high abstraction levels. The Gannet project proposes a functional...
Provided by University of Glasgow
-
White Papers
A Fast FPGA Implementation of Tate Pairing in Cryptography Over Binary Field
May 2008
Identity based cryptography schemes have opened a new territory for public key cryptography. Using identity based cryptography schemes, a sender can derive the public key of a receiver without...
Provided by University of Central Florida
-
Webcasts
Growing Lasers on Computer Chips
Feb 2011
The first time, researchers have grown lasers from high-performance materials directly on silicon. Bringing together electrical and optical components on computer chips would speed data transfer...
Provided by MIT
-
Webcasts
ProcessorPM Power Management Video
Jan 2011
Take the first step to integrate multiple processor power management devices and improve system reliability by watching this 5 minutes webcast. ProcessorPM devices are the perfect companion for...
Provided by Lattice Semiconductor
-
White Papers
MIRA: A Multi-Layered On-Chip Interconnect Router Architecture
Apr 2008
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology. However,...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Performance Analysis of Software to Hardware Task Migration in Codesign
Jan 2010
The complexity of multimedia applications in terms of intensity of computation and heterogeneity of treated data led the designers to embark them on multiprocessor systems on chip. The complexity...
Provided by International Journal of Computer Science Issues
-
White Papers
Bilateral Testing of Nano-Scale Fault-Tolerant Circuits
Jan 2009
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. Because...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
High Speed 1-Bit Bypass Adder Design for Low Precision Additions
Jul 2007
In this paper, the authors propose a high speed adder which is adopted for the reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture adopts...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
FleXilicon Architecture and Its VLSI Implementation
Aug 2009
In this paper, the authors present a new coarse-grained reconfigurable architecture called FleXilicon for multimedia and wireless communications, which improves resource utilization and achieves a...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
High Speed Channel Coding Architectures for the Uncoordinated or Channel
Jan 2011
Though it promises high bandwidths, the optical medium is not popular in local area networks. This is because current optical networks do not offer the ease of use and setup that an uncoordinated...
Provided by UC Regents
-
White Papers
Design and Performance Analysis of Efficient Bus Arbitration Schemes for On-Chip Shared Bus Multi-Processor SoC
Sep 2008
In the resource sharing mechanism of multi-processor SoC, the on-chip communication architecture plays an important role and directly affects the performance of SoC. The traditional shared bus...
Provided by G.H. Raisoni College of Engineering
-
White Papers
Using Multiple Compacted Responses to Diagnose Scan Response Errors During Testing
Jan 2011
Scan test vector and response volume are becoming problematic, and in industrial designs are complicated by the presence of unknown values in test responses. Recent work has addressed this problem...
Provided by University of Illinois
-
White Papers
Perfect Difference Network for Network-on-Chip Architecture
Dec 2009
Network-on-Chip (NoC) is a new paradigm for designing core based System-on-Chip. Network-on-Chip has been proposed as a solution for addressing the design challenges of future high performance...
Provided by Bapurao Deshmukh College of Engineering
-
White Papers
Optimal Runtime Reconfiguration Strategies for Systolic Arrays
Oct 2009
Many computation kernels that analyze large data streams can be accelerated by converting their recurrences to parallel systolic arrays. Application domains such as bioinformatics seek to minimize...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Efficient Runtime Performance Monitoring of FPGA-based Applications
May 2009
Embedded computing platforms have long incorporated non-traditional architectures (e.g., FPGAs, ASICs) to combat the diminishing returns of Moore's Law as applied to traditional processors. These...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Determining Covers in Combinational Circuits
May 2011
In this paper the authors propose a procedure for determining 0 - or 1 - cover of an arbitrary line in a combinational circuit. When determining a cover they do not need Boolean expression for the...
Provided by International Journal of Computer Science Issues
-
White Papers
Layered Switching for Networks on Chip
Jun 2007
The authors present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To show the...
Provided by Association for Computing Machinery
-
White Papers
FPGA-Based Particle Recognition in the HADES Experiment
Nov 2010
Modern FPGA technologies are often employed in nuclear and particle physics experimental facilities to accelerate application-specific computation. The authors present the particle recognition...
Provided by KTH
-
White Papers
Network Calculus Applied to Verification of Memory Access Performance in SoCs
Aug 2007
SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes the performance of...
Provided by KTH - Royal Institute of Technology
-
White Papers
Slot Allocation Using Logical Networks for TDM Virtual-Circuit Configuration for Network-on-Chip
Aug 2007
Configuring Time-Division-Multiplexing (TDM) Virtual Circuits (VCs) for network-on-chip must guarantee conflict freedom for overlapping VCs besides allocating sufficient time slots to them. These...
Provided by KTH - Royal Institute of Technology
-
White Papers
Hardware/Software Co-Design of a General-Purpose Computation Platform in Particle Physics
Oct 2007
In this paper the authors present a hardware/software co-design based computation platform for online data processing in particle physical experiments. Their goal is to ease and accelerate the...
Provided by Giessen University
-
White Papers
FPGA-Based Adaptive Computing for Correlated Multi-Stream Processing
Dec 2009
In conventional static implementations for correlated streaming applications, computing resources may be inefficiently utilized since multiple stream processors may supply their sub-results at...
Provided by KTH Royal Institute of Technology
-
White Papers
Development and Evaluation of a Memory Consistency and Cache Coherence Protocol for the Nocsim NoC Simulator
Feb 2008
Networks on Chip (NoC) have started to replace conventional buses, especially in systems on chip and distributed systems. In a typical system with a bus, cache coherency and memory consistency...
Provided by KTH - Royal Institute of Technology
-
White Papers
Inter-Process Communication Using Pipes in FPGA-Based Adaptive Computing
Apr 2010
In FPGA-based adaptive computing, Inter-Process Communications (IPC) are required to exchange information among hardware processes which time-multiplex the resources in a same reconfigurable...
Provided by KTH Royal Institute of Technology
-
White Papers
Towards Open Network-on-Chip Benchmarks
Mar 2009
Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challenge which has...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Comparative Analysis of Transient-Fault Tolerant Schemes for Network on Chips
Jun 2009
Network on a Chip (NoC) has been proposed as a viable solution to counter the inefficiency of buses in the current VLSI on-chip interconnects. However, as the silicon chip accommodates more...
Provided by Institute of Management Sciences
-
White Papers
SML-Sys: A Functional Framework With Multiple Models of Computation for Modeling Heterogeneous System
Feb 2008
System-on-Chip and other complex distributed hardware/software systems contain heterogeneous components. High-level modeling of such systems require frameworks that provide designers with the...
Provided by KTH - Royal Institute of Technology
-
White Papers
Cluster-Based Simulated Annealing for Mapping Cores Onto 2D Mesh Networks on Chip
Mar 2008
In Network-on-Chip (NoC) application design, core-to-node mapping is an important but intractable optimization problem. In the paper, the authors use simulated annealing to tackle the mapping...
Provided by KTH Royal Institute of Technology
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White Papers
System-on-an-FPGA Design for Real-Time Particle Track Recognition and Reconstruction in Physics Experiments
Jun 2008
In particle physics experiments, the momenta of charged particles are studied by observing their deflection in a magnetic field. Dedicated detectors measure the particle tracks and complex...
Provided by KTH - Royal Institute of Technology
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White Papers
Energy Efficient Streaming Applications With Guaranteed Throughput on MPSoCs
Oct 2008
In this paper the authors present a design space exploration flow to achieve energy efficiency for streaming applications on MPSoCs while meeting the specified throughput constraints. The public...
Provided by Association for Computing Machinery
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White Papers
Atca-Based Computation Platform for Data Acquisition and Triggering in Particle Physics Experiments
Jun 2008
ATCA-based computation platform for data acquisition and trigger applications in nuclear and particle physics experiments has been developed. Each Compute Node (CN) which appears as a Field...
Provided by KTH - Royal Institute of Technology
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White Papers
Implementation of a DLI-Guard Using the AMBA AXI Protocol for Network-on-Chip
Dec 2008
Nowdays, the integration of several system components or IP blocks, such as processors, DSP units and memories on one chip is overwhelming the industry. The method of integrating several...
Provided by KTH - Royal Institute of Technology
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White Papers
Generalization of Slot Table Size for Virtual Circuits on Nostrum Networks on Chip
Jun 2008
Since the late 1990's, the trend of integrated circuit design has been integrating several system components or IP blocks, such as processors and memories, on one chip. This is referred to the...
Provided by KTH - Royal Institute of Technology
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White Papers
Design Space Exploration of Field Programmable Counter Arrays and Their Integration With FPGAs
Jul 2008
Field Programmable Counter Arrays (FPCAs) have been recently introduced to close the gap between FPGA and ASICs for arithmetic dominated applications. FPCAs are reconfigurable lattices that can be...
Provided by KTH - Royal Institute of Technology
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White Papers
TDM Virtual-Circuit Configuration for Network-on-Chip
Oct 2007
In Network-on-Chip (NoC), Time-Division-Multiplexing (TDM) Virtual Circuits (VCs) have been proposed to satisfy the Quality-of-Service requirements of applications. TDM VC is a connection-oriented...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Reducing FPGA Reconfiguration Time Overhead Using Virtual Configurations
Apr 2010
Reconfiguration time overhead is a critical factor in determining the system performance of FPGA dynamically reconfigurable designs. To reduce the reconfiguration overhead, the most...
Provided by KTH Royal Institute of Technology
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Webcasts
ProcessorPM Power Management Video
Jan 2011
Take the first step to integrate multiple processor power management devices and improve system reliability by watching this 5 minutes webcast. ProcessorPM devices are the perfect companion for...
Provided by Lattice Semiconductor
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Webcasts
Growing Lasers on Computer Chips
Feb 2011
The first time, researchers have grown lasers from high-performance materials directly on silicon. Bringing together electrical and optical components on computer chips would speed data transfer...
Provided by MIT
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White Papers
A Fast FPGA Implementation of Tate Pairing in Cryptography Over Binary Field
May 2008
Identity based cryptography schemes have opened a new territory for public key cryptography. Using identity based cryptography schemes, a sender can derive the public key of a receiver without...
Provided by University of Central Florida
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White Papers
A Formal Semantics for Control and Data Flow in the Gannet Service-Based System-on-Chip Architecture
May 2008
There is a growing demand for solutions which allow the design of large and complex reconfigurable Systems-on-Chip (SoC) at high abstraction levels. The Gannet project proposes a functional...
Provided by University of Glasgow
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White Papers
Qnet: A Modular Architecture for Reconfigurable Computing
May 2008
A packet-switched network architecture named Qnet and programming interface is presented that simplifies the integration of reconfigurable computing modules within a Field Programmable Gate Array...
Provided by Brigham Young University
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White Papers
A Comparison of Traditional On-Chip Interconnects With Network-on-Chip Architecture
May 2008
The authors have investigated the Network-on-Chip (NOC) as an emerging on-chip interconnects technology, to understand and compare its impact on global communication delays, and power consumption...
Provided by California State University
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White Papers
Optimal Dynamic Routing and Flow Control in Interconnection Networks on Chip
May 2008
There has been a lot of work done on NoCs to reduce latency, power consumption and congestion control. In this paper the authors have proposed a dynamic routing algorithm with a conducive flow...
Provided by Jaypee University of Information Technology
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White Papers
New Approach for Inter Networks - On - Chip Communication in Networks - In - Package
May 2008
Networks-in-Package (NiP) is a solution for inter Networks-on-Chip (NoC) communication, where power dissipation, performance, and size of processing package are the major factors. NiP is a group...
Provided by Jaypee University of Information Technology
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