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asics - chip sets
(387 results)-
White Papers
New Approach for Inter Networks - On - Chip Communication in Networks - In - Package
May 2008
Networks-in-Package (NiP) is a solution for inter Networks-on-Chip (NoC) communication, where power dissipation, performance, and size of processing package are the major factors. NiP is a group...
Provided by Jaypee University of Information Technology
-
Whitepapers
Fast and Compact ASIC Implementation of SFlash New Signature Scheme
Oct 2009
The idea of using multivariate polynomials as public keys has attracted several cryptographers, SFlash signature scheme is a variant of the Matsumoto and Imai multivariate public Key cryptosystem...
Provided by Science and Development Network (SciDev.Net)
-
Whitepapers
Multiplierless FIR Filter Implementation on FPGA
May 2012
Area complexity in the algorithm of Finite Impulse Response (FIR) filter is mainly caused by multipliers. Among the multiplier-less techniques of FIR filter, Distributed Arithmetic is most...
Provided by International Journal of Information and Electronics Engineering
-
Whitepapers
Effect of Electrostatic Discharge on Digital and Analog Circuits
Aug 2012
A comparative study of the effects of ElectroStatic Discharge (ESD) on digital and analog circuits is carried out. Direct and Indirect discharge is performed on the circuit having both analog and...
Provided by IOSR Journal of Engineering
-
Whitepapers
A Multiport Theory of Communications
Jan 2010
Electro-magnetics provides the ground for a physical theory of communications, while information theory and signal theory approach the problem from a purely mathematical point of view....
Provided by Institute of Electrical & Electronic Engineers
-
Whitepapers
Toward a Circuit Theory of Communication
Jul 2010
Electromagnetic field theory provides the physics of radio communications, while information theory approaches the problem from a purely mathematical point of view. While there is a law of...
Provided by Institute of Electrical & Electronic Engineers
-
Whitepapers
Design and Implementation of Viterbi Encoder and Decoder Using FPGA
Jun 2012
In this paper, the authors present an implementation of the Viterbi algorithm using the Hardware Description Language and Implemented on FPGA. They begin with a description of the algorithm....
Provided by International Journal of Engineering and Advanced Technology (IJEAT)
-
Whitepapers
Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs
Feb 2012
Many True Random Numbers Generators (TRNG) use jittery clocks generated in ring oscillators as a source of entropy. This is especially the case in Field Programmable Gate Arrays (FPGA), where...
Provided by INRIA
-
Whitepapers
SysGen Architecture for Visual Information Hiding Framework
Mar 2012
The development time and cost for DSP solution have been improved significantly due to proliferation of rapid prototyping tools such as MATLAB-Simulink and Xilinx System Generator (SysGen). The...
Provided by International Journal of Emerging Technology and Advanced Engineering (IJETAE)
-
Whitepapers
Digital Clock Frequency Multiplier Using Floating Point Arithmetic
Aug 2012
A digital clock frequency multiplier using floating point arithmetic, which generates the output clock with zero frequency error has been presented. The circuit has an unbounded multiplication...
Provided by International Journal of Engineering Research and Development (IJERD)
-
Whitepapers
Design and Synthesis of a Field Programmable CRC Circuit Architecture
Jul 2011
The design and implementation of a programmable Cyclic Redundancy Check (CRC) computation circuit architecture, suitable for deployment in network related System-on-Chips (SoCs) is presented. The...
Provided by International Journal of Engineering Research and Applications (IJERA)
-
Whitepapers
Module Based and Difference Based Implementation of Partial Reconfiguration on FPGA: A Review
Nov 2011
Dynamically adaptable computing systems are promising research area at developing systems which can adapt to changes in their environment while executing. The premisses for such systems are...
Provided by International Journal of Engineering Research and Applications (IJERA)
-
Whitepapers
Flip-Flop Circuit Families: Comparison of Layout and Topology for Low Power VLSI Circuits
Nov 2011
The pertinent choice of flip-flop topologies is an essential importance in the design of VLSI integrated circuits for high speed and high performance CMOS circuits. Understanding the suitability...
Provided by International Journal of Engineering Research and Applications (IJERA)
-
Whitepapers
Repair Analysis for Embedded Memories Using Block-Based Redundancy Architecture
Jul 2012
Capacity and density of embedded memories have rapidly increased therefore they have higher probability of faults. As a result, yield of system-on-a-chip designs with embedded memories drops....
Provided by International Association of Engineers
-
Whitepapers
Design and Analysis of Finite Impulse Response Using G Ate Diffusion Input (GDI) Circuits
Jul 2011
Integrated Circuits technology advancements have consistently migrated to smaller feature sizes over the last four decades years, forcing more functional circuits to be placed on each chip. The...
Provided by Dynamic Publishers
-
Whitepapers
FPGA-Based Verification Methodology of SOC-Type CMOS Image Signal Processor
Oct 2009
This paper describes a FPGA-based verification methodology for the Image Signal Processor (ISP) of System-on-Chip (SoC) type CMOS image sensor. To make a verification environment, the complete...
Provided by Institute of Electrical & Electronic Engineers
-
Whitepapers
ASIC and FPGA Implementation Strategies for Model Predictive Control
Jun 2009
Model Predictive Control (MPC) techniques have recently enjoyed an upsurge of interest within the automatic control community, due to their ability to handle non-linear systems and constraints on...
Provided by University of New York in Prague
-
Whitepapers
ASIC Implementation of Scalable Encryption Algorithm Using Efficient Modular Adders
Mar 2012
Resource constrained encryption does not have an extensive history in symmetric cryptography. Examples of recent lightweight block ciphers are HIGHT and PRESENT. However, both of them do not...
Provided by EuroJournals
-
Whitepapers
Simulation Based Multifunctional MOS Device by Externally Controlled Gate Width
Aug 2011
The world's demand for high-speed devices and equipments are growing very drastically. Every individual researcher in all country is marching towards, to achieve it .The role of Design Engineer...
Provided by EuroJournals
-
Whitepapers
ASIC Implementation of Modified Faster Carry Save Adder
Nov 2010
Digital adders are the core block of DSP processors. The final Carry Propagation Adder (CPA) structure of many adders constitutes high carry propagation delay and this delay reduces the overall...
Provided by EuroJournals
-
Whitepapers
Design and ASIC Implementation of Root Raised Cosine Filter
Jun 2009
Raised cosine filter is a FIR filter that can be used to counter many problems of communication such as the Inter symbol interference. The rectangular pulse occupies a large bandwidth so an...
Provided by EuroJournals
-
Whitepapers
FPGA Realization of Open/Short Test on IC
Feb 2008
IC (Integrated Circuitry) testing requires the very advanced and sophisticated Advance Test Equipment (ATE) that costs multimillion USD. The cost of IC testing is increasing yearly and it will...
Provided by NORTH ATLANTIC UNIVERSITY UNION
-
Whitepapers
VHDL Simulation of Reset Automatic Block, 64bit Latch Block, and Test Complete Blocks ForPD Detection Circuit System Using FPGA
Mar 2012
This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and...
Provided by International Journal of Communications and Engineering
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Whitepapers
Efficient Weighted Pattern Generation Technique With Low Hardware Overhead
Jan 2013
Weighted pseudorandom Built-In Self Test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets...
Provided by The World
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Whitepapers
Design and Verification of Performance of 32 Bit High Speed Truncation-Error -Tolerant Adder
Aug 2012
In this paper, the authors have proposed an architecture for high speed Truncation Adder Algorithm. In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By...
Provided by The World
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Whitepapers
Partial Matching Mixed Mode BIST Design for Test Data Reduction
Mar 2012
A mixed-mode Built-In Self-Test (BIST) approach that deploys two new techniques is presented in this paper. Partial pattern matching allows the reduction of the number of patterns used for...
Provided by International Journal of Communications and Engineering
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Whitepapers
BPSK Transmitter Design Using FPGA With DAC and Pulse Shaping Filter to Minimize Inter-Symbol Interference(ISI)
Feb 2013
In contrast to the sophisticated implementation of Binary Phase Shift Keying (BPSK) transmitter using Application Specific Integrated Circuit (ASIC), mixer, and Local Oscillator(LO) for carrier...
Provided by IOSR Journal of Engineering
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Whitepapers
Three Dimensional-Chips
Oct 2012
This paper illustrates the performance advantages of 3D integrated circuits with two specific examples, namely 3D-FPGA and 3D-SRAM. Three-dimensional Chip (3D IC, 3D-IC, or 3-D IC) is a chip in...
Provided by IOSR Journal of Engineering
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Whitepapers
Folded Architecture of Scheduler for Area Optimization in On-Chip Switch Fabric
Mar 2011
As the feature sizes of the manufacturing processes are constantly shrinking, the possibility and demand for more functionality on a single chip goes up. This can lead to many problems e.g. as the...
Provided by Science and Development Network (SciDev.Net)
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Whitepapers
Efficient DPA Attacks on AES Hardware Implementations
Feb 2008
In this paper, the authors present an effective way to enhance power analysis attacks on AES hardware implementations. The proposed attack adopts hamming difference of intermediate results as...
Provided by Scientific Research
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White Papers
Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits
Feb 2011
This paper presents an in-depth study of Mesh-of-Tree (MoT) topology and its application in Network-on-Chip (NoC) design for both 2-D and 3-D ICs. The performance and cost of the MoT network have...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Physical Synthesis With Clock-Network Optimization for Large Systems on Chips
Aug 2011
In this paper, the authors address a known hard problem - closing the gap between custom and semicustom VLSI design styles and the ASIC VLSI design style - critical to the effective design of...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Design and Application of IP Core in SoC Technology
Apr 2010
SoC (System on Chip) design is a new development of design technology under the design of dedicated chip ASICs (Application Specific Integrated Circuits). It is an integrated chip design method...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Mercury BLASTN Biosequence Similarity Search System: Technical Reference Guide
May 2011
The Mercury BLASTN application is a hybrid hardware-software implementation of DNA-to-DNA sequence comparison. It presents an interface similar to that of NCBI BLASTN 2.2 (and indeed uses much of...
Provided by University of Washington
-
White Papers
Split and Merge Functions for Supporting Multiple Processing Pipelines in Mercury BLASTN
May 2010
Biosequence similarity search is an important application in computational biology. Mercury BLASTN, an FPGA-based implementation of BLAST for DNA, is one of the alternatives for fast DNA sequence...
Provided by University of Washington
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White Papers
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
May 2011
Pre-bond testing of 3-D stacked Integrated Circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability because manufacturers...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing
Sep 2009
Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays. With...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems
Feb 2011
The design space of FPGA-based processor systems is huge, because many parameters can be modified at design- and run-time to achieve an efficient system solution in terms of performance, power and...
Provided by Hindawi Publishing
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White Papers
Experiment Centric Teaching for Reconfigurable Processors
Dec 2010
This paper presents a setup for teaching configware to master students. The authors' approach focuses on experiment and leaning-by-doing while being supported by research activity. The central...
Provided by Hindawi Publishing
-
White Papers
A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs
Jan 2011
In FPGA embedded systems, designers usually have to make a compromise between numerical precision and logical resources. Scientific computations in particular, usually require highly accurate...
Provided by Hindawi Publishing
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White Papers
Reducing FPGA Reconfiguration Time Overhead Using Virtual Configurations
Apr 2010
Reconfiguration time overhead is a critical factor in determining the system performance of FPGA dynamically reconfigurable designs. To reduce the reconfiguration overhead, the most...
Provided by KTH Royal Institute of Technology
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White Papers
TDM Virtual-Circuit Configuration for Network-on-Chip
Oct 2007
In Network-on-Chip (NoC), Time-Division-Multiplexing (TDM) Virtual Circuits (VCs) have been proposed to satisfy the Quality-of-Service requirements of applications. TDM VC is a connection-oriented...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Design Space Exploration of Field Programmable Counter Arrays and Their Integration With FPGAs
Jul 2008
Field Programmable Counter Arrays (FPCAs) have been recently introduced to close the gap between FPGA and ASICs for arithmetic dominated applications. FPCAs are reconfigurable lattices that can be...
Provided by KTH - Royal Institute of Technology
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White Papers
Generalization of Slot Table Size for Virtual Circuits on Nostrum Networks on Chip
Jun 2008
Since the late 1990's, the trend of integrated circuit design has been integrating several system components or IP blocks, such as processors and memories, on one chip. This is referred to the...
Provided by KTH - Royal Institute of Technology
-
White Papers
Implementation of a DLI-Guard Using the AMBA AXI Protocol for Network-on-Chip
Dec 2008
Nowdays, the integration of several system components or IP blocks, such as processors, DSP units and memories on one chip is overwhelming the industry. The method of integrating several...
Provided by KTH - Royal Institute of Technology
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White Papers
Atca-Based Computation Platform for Data Acquisition and Triggering in Particle Physics Experiments
Jun 2008
ATCA-based computation platform for data acquisition and trigger applications in nuclear and particle physics experiments has been developed. Each Compute Node (CN) which appears as a Field...
Provided by KTH - Royal Institute of Technology
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White Papers
Energy Efficient Streaming Applications With Guaranteed Throughput on MPSoCs
Oct 2008
In this paper the authors present a design space exploration flow to achieve energy efficiency for streaming applications on MPSoCs while meeting the specified throughput constraints. The public...
Provided by Association for Computing Machinery
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White Papers
System-on-an-FPGA Design for Real-Time Particle Track Recognition and Reconstruction in Physics Experiments
Jun 2008
In particle physics experiments, the momenta of charged particles are studied by observing their deflection in a magnetic field. Dedicated detectors measure the particle tracks and complex...
Provided by KTH - Royal Institute of Technology
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White Papers
Cluster-Based Simulated Annealing for Mapping Cores Onto 2D Mesh Networks on Chip
Mar 2008
In Network-on-Chip (NoC) application design, core-to-node mapping is an important but intractable optimization problem. In the paper, the authors use simulated annealing to tackle the mapping...
Provided by KTH Royal Institute of Technology
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White Papers
SML-Sys: A Functional Framework With Multiple Models of Computation for Modeling Heterogeneous System
Feb 2008
System-on-Chip and other complex distributed hardware/software systems contain heterogeneous components. High-level modeling of such systems require frameworks that provide designers with the...
Provided by KTH - Royal Institute of Technology
-
White Papers
Comparative Analysis of Transient-Fault Tolerant Schemes for Network on Chips
Jun 2009
Network on a Chip (NoC) has been proposed as a viable solution to counter the inefficiency of buses in the current VLSI on-chip interconnects. However, as the silicon chip accommodates more...
Provided by Institute of Management Sciences
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White Papers
Towards Open Network-on-Chip Benchmarks
Mar 2009
Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challenge which has...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Inter-Process Communication Using Pipes in FPGA-Based Adaptive Computing
Apr 2010
In FPGA-based adaptive computing, Inter-Process Communications (IPC) are required to exchange information among hardware processes which time-multiplex the resources in a same reconfigurable...
Provided by KTH Royal Institute of Technology
-
White Papers
Development and Evaluation of a Memory Consistency and Cache Coherence Protocol for the Nocsim NoC Simulator
Feb 2008
Networks on Chip (NoC) have started to replace conventional buses, especially in systems on chip and distributed systems. In a typical system with a bus, cache coherency and memory consistency...
Provided by KTH - Royal Institute of Technology
-
White Papers
FPGA-Based Adaptive Computing for Correlated Multi-Stream Processing
Dec 2009
In conventional static implementations for correlated streaming applications, computing resources may be inefficiently utilized since multiple stream processors may supply their sub-results at...
Provided by KTH Royal Institute of Technology
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White Papers
Hardware/Software Co-Design of a General-Purpose Computation Platform in Particle Physics
Oct 2007
In this paper the authors present a hardware/software co-design based computation platform for online data processing in particle physical experiments. Their goal is to ease and accelerate the...
Provided by Giessen University
-
White Papers
Slot Allocation Using Logical Networks for TDM Virtual-Circuit Configuration for Network-on-Chip
Aug 2007
Configuring Time-Division-Multiplexing (TDM) Virtual Circuits (VCs) for network-on-chip must guarantee conflict freedom for overlapping VCs besides allocating sufficient time slots to them. These...
Provided by KTH - Royal Institute of Technology
-
White Papers
Network Calculus Applied to Verification of Memory Access Performance in SoCs
Aug 2007
SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes the performance of...
Provided by KTH - Royal Institute of Technology
-
White Papers
FPGA-Based Particle Recognition in the HADES Experiment
Nov 2010
Modern FPGA technologies are often employed in nuclear and particle physics experimental facilities to accelerate application-specific computation. The authors present the particle recognition...
Provided by KTH
-
White Papers
Layered Switching for Networks on Chip
Jun 2007
The authors present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To show the...
Provided by Association for Computing Machinery
-
White Papers
Determining Covers in Combinational Circuits
May 2011
In this paper the authors propose a procedure for determining 0 - or 1 - cover of an arbitrary line in a combinational circuit. When determining a cover they do not need Boolean expression for the...
Provided by International Journal of Computer Science Issues
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White Papers
Efficient Runtime Performance Monitoring of FPGA-based Applications
May 2009
Embedded computing platforms have long incorporated non-traditional architectures (e.g., FPGAs, ASICs) to combat the diminishing returns of Moore's Law as applied to traditional processors. These...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Optimal Runtime Reconfiguration Strategies for Systolic Arrays
Oct 2009
Many computation kernels that analyze large data streams can be accelerated by converting their recurrences to parallel systolic arrays. Application domains such as bioinformatics seek to minimize...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Perfect Difference Network for Network-on-Chip Architecture
Dec 2009
Network-on-Chip (NoC) is a new paradigm for designing core based System-on-Chip. Network-on-Chip has been proposed as a solution for addressing the design challenges of future high performance...
Provided by Bapurao Deshmukh College of Engineering
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White Papers
Using Multiple Compacted Responses to Diagnose Scan Response Errors During Testing
Jan 2011
Scan test vector and response volume are becoming problematic, and in industrial designs are complicated by the presence of unknown values in test responses. Recent work has addressed this problem...
Provided by University of Illinois
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White Papers
Design and Performance Analysis of Efficient Bus Arbitration Schemes for On-Chip Shared Bus Multi-Processor SoC
Sep 2008
In the resource sharing mechanism of multi-processor SoC, the on-chip communication architecture plays an important role and directly affects the performance of SoC. The traditional shared bus...
Provided by G.H. Raisoni College of Engineering
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White Papers
High Speed Channel Coding Architectures for the Uncoordinated or Channel
Jan 2011
Though it promises high bandwidths, the optical medium is not popular in local area networks. This is because current optical networks do not offer the ease of use and setup that an uncoordinated...
Provided by UC Regents
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White Papers
FleXilicon Architecture and Its VLSI Implementation
Aug 2009
In this paper, the authors present a new coarse-grained reconfigurable architecture called FleXilicon for multimedia and wireless communications, which improves resource utilization and achieves a...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
High Speed 1-Bit Bypass Adder Design for Low Precision Additions
Jul 2007
In this paper, the authors propose a high speed adder which is adopted for the reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture adopts...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Bilateral Testing of Nano-Scale Fault-Tolerant Circuits
Jan 2009
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. Because...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Performance Analysis of Software to Hardware Task Migration in Codesign
Jan 2010
The complexity of multimedia applications in terms of intensity of computation and heterogeneity of treated data led the designers to embark them on multiprocessor systems on chip. The complexity...
Provided by International Journal of Computer Science Issues
-
White Papers
MIRA: A Multi-Layered On-Chip Interconnect Router Architecture
Apr 2008
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology. However,...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Development Strategy of Next Generation Singlechip Smart Inverters for Motor Control Applications
Jul 2007
In smart-power IC technologies the trend toward more functional integration is expected to intensify further, producing more compact, efficient, and user-friendly power modules. It looks that in...
Provided by Technical University of Cluj-Napoca
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White Papers
Dynamic Packet Fragmentation for Increased Virtual Channel Utilization in On-Chip Routers
Mar 2009
Conventional packet-switched on-chip routers provide good resource sharing while minimizing latencies through various techniques. A Virtual Channel (VC) is allocated on a per-packet basis and held...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Multicast Routing With Dynamic Packet Fragmentation
May 2009
Networks-on-Chip (NoCs) become a critical design factor as Chip MultiProcessors (CMPs) and Systems on a Chip (SoCs) scale up with technology. With fundamental benefits of high bandwidth and...
Provided by Association for Computing Machinery
-
White Papers
TID Damage and Annealing Response of 90 Nm Commercial-Density SRAMs
Sep 2008
The authors characterize the TID resilience and annealing response of high-density SRAMs, fabricated in 90 nm commercial processes. Results demonstrate intrinsic SRAM hardness at 300 krad(Si), but...
Provided by University of Southern California
-
White Papers
Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-Nm SRAMs
Aug 2007
A mathematical Bit Error Rate (BER) model for upsets in memories protected by Error-Correcting Codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Power-Driven Design of Router Microarchitectures in On-Chip Networks
Jan 2011
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-chip...
Provided by Princeton University
-
White Papers
Practical Off-Chip Meta-Data for Temporal Memory Streaming
Dec 2008
Prior research demonstrates that temporal memory streaming and related address-correlating prefetchers improve performance of commercial server workloads through increased memory level...
Provided by University of Michigan
-
White Papers
Don't Forget Memories - A Case Study Redesigning a Pattern Counting ASIC Circuit for FPGAs
Oct 2008
Modern embedded compute platforms increasingly contain both microprocessors and Field-Programmable Gate Arrays (FPGAs). The FPGAs may implement accelerators or other circuits to speedup...
Provided by Association for Computing Machinery
-
Whitepapers
Fast and Compact ASIC Implementation of SFlash New Signature Scheme
Oct 2009
The idea of using multivariate polynomials as public keys has attracted several cryptographers, SFlash signature scheme is a variant of the Matsumoto and Imai multivariate public Key cryptosystem...
Provided by Science and Development Network (SciDev.Net)
-
Whitepapers
Multiplierless FIR Filter Implementation on FPGA
May 2012
Area complexity in the algorithm of Finite Impulse Response (FIR) filter is mainly caused by multipliers. Among the multiplier-less techniques of FIR filter, Distributed Arithmetic is most...
Provided by International Journal of Information and Electronics Engineering
-
Whitepapers
Effect of Electrostatic Discharge on Digital and Analog Circuits
Aug 2012
A comparative study of the effects of ElectroStatic Discharge (ESD) on digital and analog circuits is carried out. Direct and Indirect discharge is performed on the circuit having both analog and...
Provided by IOSR Journal of Engineering
-
Whitepapers
A Multiport Theory of Communications
Jan 2010
Electro-magnetics provides the ground for a physical theory of communications, while information theory and signal theory approach the problem from a purely mathematical point of view....
Provided by Institute of Electrical & Electronic Engineers
-
Whitepapers
Toward a Circuit Theory of Communication
Jul 2010
Electromagnetic field theory provides the physics of radio communications, while information theory approaches the problem from a purely mathematical point of view. While there is a law of...
Provided by Institute of Electrical & Electronic Engineers
-
Whitepapers
Design and Implementation of Viterbi Encoder and Decoder Using FPGA
Jun 2012
In this paper, the authors present an implementation of the Viterbi algorithm using the Hardware Description Language and Implemented on FPGA. They begin with a description of the algorithm....
Provided by International Journal of Engineering and Advanced Technology (IJEAT)
-
Whitepapers
Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs
Feb 2012
Many True Random Numbers Generators (TRNG) use jittery clocks generated in ring oscillators as a source of entropy. This is especially the case in Field Programmable Gate Arrays (FPGA), where...
Provided by INRIA
-
Whitepapers
SysGen Architecture for Visual Information Hiding Framework
Mar 2012
The development time and cost for DSP solution have been improved significantly due to proliferation of rapid prototyping tools such as MATLAB-Simulink and Xilinx System Generator (SysGen). The...
Provided by International Journal of Emerging Technology and Advanced Engineering (IJETAE)
-
Whitepapers
Digital Clock Frequency Multiplier Using Floating Point Arithmetic
Aug 2012
A digital clock frequency multiplier using floating point arithmetic, which generates the output clock with zero frequency error has been presented. The circuit has an unbounded multiplication...
Provided by International Journal of Engineering Research and Development (IJERD)
-
Whitepapers
Design and Synthesis of a Field Programmable CRC Circuit Architecture
Jul 2011
The design and implementation of a programmable Cyclic Redundancy Check (CRC) computation circuit architecture, suitable for deployment in network related System-on-Chips (SoCs) is presented. The...
Provided by International Journal of Engineering Research and Applications (IJERA)
-
Whitepapers
Module Based and Difference Based Implementation of Partial Reconfiguration on FPGA: A Review
Nov 2011
Dynamically adaptable computing systems are promising research area at developing systems which can adapt to changes in their environment while executing. The premisses for such systems are...
Provided by International Journal of Engineering Research and Applications (IJERA)
-
Whitepapers
Flip-Flop Circuit Families: Comparison of Layout and Topology for Low Power VLSI Circuits
Nov 2011
The pertinent choice of flip-flop topologies is an essential importance in the design of VLSI integrated circuits for high speed and high performance CMOS circuits. Understanding the suitability...
Provided by International Journal of Engineering Research and Applications (IJERA)
-
Whitepapers
Repair Analysis for Embedded Memories Using Block-Based Redundancy Architecture
Jul 2012
Capacity and density of embedded memories have rapidly increased therefore they have higher probability of faults. As a result, yield of system-on-a-chip designs with embedded memories drops....
Provided by International Association of Engineers
-
Whitepapers
Design and Analysis of Finite Impulse Response Using G Ate Diffusion Input (GDI) Circuits
Jul 2011
Integrated Circuits technology advancements have consistently migrated to smaller feature sizes over the last four decades years, forcing more functional circuits to be placed on each chip. The...
Provided by Dynamic Publishers
-
Whitepapers
FPGA-Based Verification Methodology of SOC-Type CMOS Image Signal Processor
Oct 2009
This paper describes a FPGA-based verification methodology for the Image Signal Processor (ISP) of System-on-Chip (SoC) type CMOS image sensor. To make a verification environment, the complete...
Provided by Institute of Electrical & Electronic Engineers
-
Whitepapers
ASIC and FPGA Implementation Strategies for Model Predictive Control
Jun 2009
Model Predictive Control (MPC) techniques have recently enjoyed an upsurge of interest within the automatic control community, due to their ability to handle non-linear systems and constraints on...
Provided by University of New York in Prague
-
Whitepapers
ASIC Implementation of Scalable Encryption Algorithm Using Efficient Modular Adders
Mar 2012
Resource constrained encryption does not have an extensive history in symmetric cryptography. Examples of recent lightweight block ciphers are HIGHT and PRESENT. However, both of them do not...
Provided by EuroJournals
-
Whitepapers
Simulation Based Multifunctional MOS Device by Externally Controlled Gate Width
Aug 2011
The world's demand for high-speed devices and equipments are growing very drastically. Every individual researcher in all country is marching towards, to achieve it .The role of Design Engineer...
Provided by EuroJournals
-
Whitepapers
ASIC Implementation of Modified Faster Carry Save Adder
Nov 2010
Digital adders are the core block of DSP processors. The final Carry Propagation Adder (CPA) structure of many adders constitutes high carry propagation delay and this delay reduces the overall...
Provided by EuroJournals
-
Whitepapers
Design and ASIC Implementation of Root Raised Cosine Filter
Jun 2009
Raised cosine filter is a FIR filter that can be used to counter many problems of communication such as the Inter symbol interference. The rectangular pulse occupies a large bandwidth so an...
Provided by EuroJournals
-
Whitepapers
FPGA Realization of Open/Short Test on IC
Feb 2008
IC (Integrated Circuitry) testing requires the very advanced and sophisticated Advance Test Equipment (ATE) that costs multimillion USD. The cost of IC testing is increasing yearly and it will...
Provided by NORTH ATLANTIC UNIVERSITY UNION
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Whitepapers
VHDL Simulation of Reset Automatic Block, 64bit Latch Block, and Test Complete Blocks ForPD Detection Circuit System Using FPGA
Mar 2012
This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and...
Provided by International Journal of Communications and Engineering
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Whitepapers
Efficient Weighted Pattern Generation Technique With Low Hardware Overhead
Jan 2013
Weighted pseudorandom Built-In Self Test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets...
Provided by The World
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Whitepapers
Design and Verification of Performance of 32 Bit High Speed Truncation-Error -Tolerant Adder
Aug 2012
In this paper, the authors have proposed an architecture for high speed Truncation Adder Algorithm. In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By...
Provided by The World
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Whitepapers
Partial Matching Mixed Mode BIST Design for Test Data Reduction
Mar 2012
A mixed-mode Built-In Self-Test (BIST) approach that deploys two new techniques is presented in this paper. Partial pattern matching allows the reduction of the number of patterns used for...
Provided by International Journal of Communications and Engineering
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Whitepapers
BPSK Transmitter Design Using FPGA With DAC and Pulse Shaping Filter to Minimize Inter-Symbol Interference(ISI)
Feb 2013
In contrast to the sophisticated implementation of Binary Phase Shift Keying (BPSK) transmitter using Application Specific Integrated Circuit (ASIC), mixer, and Local Oscillator(LO) for carrier...
Provided by IOSR Journal of Engineering
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Whitepapers
Three Dimensional-Chips
Oct 2012
This paper illustrates the performance advantages of 3D integrated circuits with two specific examples, namely 3D-FPGA and 3D-SRAM. Three-dimensional Chip (3D IC, 3D-IC, or 3-D IC) is a chip in...
Provided by IOSR Journal of Engineering
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Whitepapers
Folded Architecture of Scheduler for Area Optimization in On-Chip Switch Fabric
Mar 2011
As the feature sizes of the manufacturing processes are constantly shrinking, the possibility and demand for more functionality on a single chip goes up. This can lead to many problems e.g. as the...
Provided by Science and Development Network (SciDev.Net)
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Whitepapers
Efficient DPA Attacks on AES Hardware Implementations
Feb 2008
In this paper, the authors present an effective way to enhance power analysis attacks on AES hardware implementations. The proposed attack adopts hamming difference of intermediate results as...
Provided by Scientific Research
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White Papers
Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits
Feb 2011
This paper presents an in-depth study of Mesh-of-Tree (MoT) topology and its application in Network-on-Chip (NoC) design for both 2-D and 3-D ICs. The performance and cost of the MoT network have...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Physical Synthesis With Clock-Network Optimization for Large Systems on Chips
Aug 2011
In this paper, the authors address a known hard problem - closing the gap between custom and semicustom VLSI design styles and the ASIC VLSI design style - critical to the effective design of...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Design and Application of IP Core in SoC Technology
Apr 2010
SoC (System on Chip) design is a new development of design technology under the design of dedicated chip ASICs (Application Specific Integrated Circuits). It is an integrated chip design method...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Mercury BLASTN Biosequence Similarity Search System: Technical Reference Guide
May 2011
The Mercury BLASTN application is a hybrid hardware-software implementation of DNA-to-DNA sequence comparison. It presents an interface similar to that of NCBI BLASTN 2.2 (and indeed uses much of...
Provided by University of Washington
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White Papers
Split and Merge Functions for Supporting Multiple Processing Pipelines in Mercury BLASTN
May 2010
Biosequence similarity search is an important application in computational biology. Mercury BLASTN, an FPGA-based implementation of BLAST for DNA, is one of the alternatives for fast DNA sequence...
Provided by University of Washington
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White Papers
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
May 2011
Pre-bond testing of 3-D stacked Integrated Circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability because manufacturers...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing
Sep 2009
Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays. With...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems
Feb 2011
The design space of FPGA-based processor systems is huge, because many parameters can be modified at design- and run-time to achieve an efficient system solution in terms of performance, power and...
Provided by Hindawi Publishing
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White Papers
Experiment Centric Teaching for Reconfigurable Processors
Dec 2010
This paper presents a setup for teaching configware to master students. The authors' approach focuses on experiment and leaning-by-doing while being supported by research activity. The central...
Provided by Hindawi Publishing
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White Papers
A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs
Jan 2011
In FPGA embedded systems, designers usually have to make a compromise between numerical precision and logical resources. Scientific computations in particular, usually require highly accurate...
Provided by Hindawi Publishing
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White Papers
A Vector-Like Reconfigurable Floating-Point Unit for the Logarithm
Jan 2011
The use of reconfigurable computing for accelerating floating-point intensive codes is becoming common due to the availability of DSPs in new-generation FPGAs. The authors present the design of an...
Provided by Hindawi Publishing
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