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asics - chip sets
(387 results)-
White Papers
A Vector-Like Reconfigurable Floating-Point Unit for the Logarithm
Jan 2011
The use of reconfigurable computing for accelerating floating-point intensive codes is becoming common due to the availability of DSPs in new-generation FPGAs. The authors present the design of an...
Provided by Hindawi Publishing
-
White Papers
On Self-Timed Circuits in Real-Time Systems
Jan 2011
While asynchronous logic has many potential advantages compared to traditional synchronous designs, one of the major drawbacks is its unpredictability with respect to temporal behavior. Having no...
Provided by Hindawi Publishing
-
White Papers
An FPGA-Based Adaptable 200 MHz Bandwidth Channel Sounder for Wireless Communication Channel Characterisation
Jan 2011
This paper describes the development of a fast adaptable FPGA-based wide-band channel sounder with signal bandwidths of up to 200MHz and channel sampling rates up to 5.4 kHz. The application of...
Provided by Hindawi Publishing
-
White Papers
The Potential for a GPU-Like Overlay Architecture for FPGAs
Dec 2010
The authors propose a soft processor programming model and architecture inspired by Graphics Processing Units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and...
Provided by Hindawi Publishing
-
White Papers
An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads
Dec 2010
Parallel graph-oriented applications expressed in the Bulk-Synchronous Parallel (BSP) and Token Dataflow compute models generate highly-structured communication workloads from messages propagating...
Provided by Hindawi Publishing
-
White Papers
Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates
Dec 2010
The aggressive scaling of CMOS technology has increased the density and allowed the integration of multiple processors into a single chip. Although solutions based on MPSoC architectures can...
Provided by Hindawi Publishing
-
White Papers
Floorplacement for Partial Reconfigurable FPGA-Based Systems
Dec 2010
The authors presented a resource- and configuration-aware floor-placement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength. Their work...
Provided by Hindawi Publishing
-
White Papers
High-Level Synthesis of In-Circuit Assertions for Verification
Dec 2010
Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-Level Synthesis (HLS) tools have...
Provided by Hindawi Publishing
-
White Papers
FPGA Implementation for GMM-Based Speaker Identification
Nov 2010
In today's society, highly accurate personal identification systems are required. Passwords or pin numbers can be forgotten or forged and are no longer considered to offer a high level of...
Provided by Hindawi Publishing
-
White Papers
An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms
Nov 2010
The design of complex circuits as SoCs presents two great challenges to designers. One is the speeding up of system functionality modeling and the second is the implementation of the system in an...
Provided by Hindawi Publishing
-
White Papers
A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos
Oct 2010
This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation that targets high-definition videos. This design can process very high-definition videos...
Provided by Hindawi Publishing
-
White Papers
FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition
Sep 2010
A scalable large vocabulary, speaker independent speech recognition system is being developed using Hidden Markov Models (HMMs) for acoustic modeling and a Weighted Finite State Transducer (WFST)...
Provided by Hindawi Publishing
-
White Papers
Low-Complexity Online Synthesis for AMIDAR Processors
Dec 2010
Future chip technologies will change the way the authors deal with hardware design. First of all, logic resources will be available in vast amount. Furthermore, engineering specialized designs for...
Provided by Hindawi Publishing
-
White Papers
Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures
Dec 2010
Field-Programmable Gate Arrays (FPGAs) and other Reconfigurable Computing (RC) devices have been widely shown to have numerous advantages including order of magnitude performance and power...
Provided by Hindawi Publishing
-
White Papers
Reconfigurable Multiprocessor Systems: A Review
Oct 2010
Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them. This approach provides better results in terms of area, speed, and...
Provided by Hindawi Publishing
-
White Papers
Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic
Nov 2010
Dynamic Partial Reconfiguration (DPR) allows one to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, the authors present two new DPR...
Provided by Hindawi Publishing
-
White Papers
Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics
Oct 2010
FPGA design of side-channel analysis countermeasures using unmasked dual-rail with pre-charge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful...
Provided by Hindawi Publishing
-
White Papers
Mechanism of Resource Virtualization in RCS for Multitask Stream Applications
Sep 2010
Virtualization of logic, routing, and communication resources in recent FPGA devices can provide a dramatic improvement in cost-efficiency for Reconfigurable Computing systems (RCSs). The...
Provided by Hindawi Publishing
-
White Papers
3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans
Aug 2010
The authors propose new 3D 2-layer and 3-layer NoC architectures that utilize homogeneous regular mesh networks on a separate layer and one or two heterogeneous floorplanning layers. These...
Provided by Hindawi Publishing
-
White Papers
Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing
Jun 2010
This paper presents the design of a reconfigurable asynchronous computing element, called the Pulsed Quad-cell (PQ-cell), for constructing conformal computers. Conformal computers are systems with...
Provided by Hindawi Publishing
-
White Papers
New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA
Apr 2010
Currently, reconfigurable hardware devices feature a high density of heterogeneous resources to enable multitasking and offer flexibility in application needs. These concepts raise the need for...
Provided by Hindawi Publishing
-
White Papers
Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study
Feb 2010
Reconfigurable Computers (RCs) are traditional computers extended with co-processors based on reconfigurable hardware like FPGAs. Representative RC systems include SGI RC100, SRC-6, and Cray XD1....
Provided by Hindawi Publishing
-
White Papers
Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs
Jan 2010
The authors present a method for implementing high speed Finite Impulse Response (FIR) filters on Field Programmable Gate Arrays (FPGAs). Their algorithm is a multiplierless technique where fixed...
Provided by Hindawi Publishing
-
White Papers
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures
Nov 2009
The dynamic and partial reconfiguration of FPGAs enables the dynamic placement in reconfigurable zones of the tasks that describe an application. However, the dynamic management of the tasks...
Provided by Hindawi Publishing
-
White Papers
Power Characterisation for Fine-Grain Reconfigurable Fabrics
Oct 2009
This paper proposes a benchmarking methodology for characterising the power consumption of the fine-grain fabric in reconfigurable architectures. This methodology is part of the GroundHog 2009...
Provided by Hindawi Publishing
-
White Papers
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms
Dec 2009
This paper presents the OveRSoC project. The objective is to develop an exploration and validation methodology of embedded Real Time Operating Systems (RTOSs) for Reconfigurable...
Provided by Hindawi Publishing
-
White Papers
An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures
Sep 2009
This paper proposes an exact ILP formulation for the task scheduling problem on a 2D dynamically and partially reconfigurable architecture. The authors' approach takes physical constraints of the...
Provided by Hindawi Publishing
-
White Papers
A Hardware Filesystem Implementation with Multidisk Support
Aug 2009
Modern High-End Computing systems frequently include FPGAs as compute accelerators. These programmable logic devices now support disk controller IP cores which offer the ability to introduce new,...
Provided by Hindawi Publishing
-
White Papers
FPGA Interconnect Topologies Exploration
Jul 2009
This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest...
Provided by Hindawi Publishing
-
White Papers
Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings
Jun 2009
A True Random Number Generator (TRNG) is an important component in cryptographic systems. Designing a fast and secure TRNG in an FPGA is a challenging task. In this paper, the authors analyze the...
Provided by Hindawi Publishing
-
White Papers
A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips
May 2009
The authors present a heuristic algorithm for the run-time distribution of task sets in a homogeneous Multiprocessor network-on-chip. The algorithm is itself distributed over the processors and...
Provided by Hindawi Publishing
-
White Papers
A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation
May 2009
Channel estimation in wireless communication systems is usually accomplished by inserting, along with the information, a series of known symbols, whose analysis is used to define the parameters of...
Provided by Hindawi Publishing
-
White Papers
An Adaptive Message Passing MPSoC Framework
Apr 2009
Multi-Processor Systems-on-Chips (MPSoCs) offer superior performance while maintaining flexibility and reusability thanks to software oriented personalization. While most MPSoCs are today...
Provided by Hindawi Publishing
-
White Papers
A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime
May 2009
Run-time reconfigurable system-on-chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying...
Provided by Hindawi Publishing
-
White Papers
Multilevel Simulation of Heterogeneous Reconfigurable Platforms
Apr 2009
This paper presents a general system-level simulation and testing methodology for reconfigurable System-on-Chips, starting from behavioral specifications of system activities to multilevel...
Provided by Hindawi Publishing
-
White Papers
A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks
Apr 2009
FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs) applications, offering the key requirement of reconfigurability. However,...
Provided by Hindawi Publishing
-
White Papers
High level modeling of Dynamic Reconfigurable FPGAs
Mar 2009
As System-on-Chip (SoC) based embedded systems have become a defacto industry standard, their overall design complexity has increased exponentially in recent years, necessitating the introduction...
Provided by Hindawi Publishing
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White Papers
Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs
Jan 2009
Modern FPGAs contain embedded DSP blocks, which can be configured as multipliers with more than one possible size. FPGA-based designs using these multigranular embedded blocks become more...
Provided by Hindawi Publishing
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White Papers
The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units
Oct 2008
This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and...
Provided by Hindawi Publishing
-
White Papers
Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration
Nov 2008
In real-time signal processing, a single application often has multiple computationally intensive kernels that can benefit from acceleration using custom or reconfigurable hardware platforms, such...
Provided by Hindawi Publishing
-
White Papers
A Statistical Approach to Contention Modeling for High-Level Heterogeneous Multiprocessor Simulation
Jan 2011
Single chip systems featuring multiple heterogeneous processors and a variety of communication and memory architectures have emerged to satisfy the demand for networking, handheld computing, and...
Provided by Carnegie Mellon University
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White Papers
The Importance of Including Dependencies in Trace Based Performance Analysis of On-Chip Networks
Dec 2009
With the advent of large scale chip-level multiprocesssors, there is renewed interest in the design and analysis of on-chip networks. The use of full system simulation is the most accurate way to...
Provided by UC Regents
-
White Papers
DAMQ-Based Schemes for Efficiently Using the Buffer Spaces of a NoC Router
Oct 2009
In this paper the authors present high performance Dynamically Allocated Multi-Queue (DAMQ) buffer schemes for fault tolerance systems on chip applications that require an interconnection network....
Provided by Islamic Azad University
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White Papers
Evaluating GPUs for Network Packet Signature Matching
Feb 2009
Modern network devices employ deep packet inspection to enable sophisticated services such as intrusion detection, traffic shaping, and load balancing. At the heart of such services is a signature...
Provided by University of Wisconsin
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White Papers
Performance Benefits of Monolithically Stacked 3-D FPGA
Mar 2010
The performance benefits of a monolithically stacked Three-Dimensional (3-D) Field-Programmable Gate Array (FPGA), whereby the programming overhead of an FPGA is stacked on top of a standard CMOS...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Schedulability Analysis for Fixed Priority Wormhole Switching in On-Chip Networks
Nov 2008
In this paper, the authors discuss a real-time on-chip communication service with a priority-based wormhole switching policy. A novel off-line schedulability analysis approach and its extension...
Provided by University of York
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White Papers
A Method to Solve the Probe Load Effection in the High Speed Digital Circuit
Jun 2009
The measuring result has much business with the performance of the oscilloscope probe. First the authors analyze the probe load effection, and then present a method to solve the problem by using...
Provided by Tianjin Polytechnic University
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White Papers
Practical Approach to Programmable Analog Circuits With Memristors
Jan 2010
The authors suggest an approach to use memristors (resistors with memory) in programmable analog circuits. The idea consists in a circuit design in which low voltages are applied to memristors...
Provided by University of South Carolina
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White Papers
Comparing Memory Systems for Chip Multiprocessors
Jun 2007
There are two basic models for the on-chip memory in CMP systems: Hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison of the two models...
Provided by Association for Computing Machinery
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White Papers
Polymorphic On-Chip Networks
Mar 2008
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. The authors begin this...
Provided by University of Washington
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White Papers
A Flexible Design Flow for Software IP Binding in FPGA
Sep 2010
SoftWare Intellectual Property (SWIP) is a critical component of increasingly complex Field Programmable Gate Arrays (FPGA)-based System-On-Chip (SOC) designs. As a result, developers want to...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Improved Ring Oscillator PUF: An FPGA-Friendly Secure Primitive
Oct 2010
In this paper, the authors analyze Ring Oscillator (RO) based Physical Unclonable Function (PUF) on FPGAs. They show that the systematic process variation adversely affects the ability of the...
Provided by International Association for Cryptologic Research
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White Papers
An Analysis of Delay Based PUF Implementations on FPGA
Mar 2010
Physical Unclonable Functions promise cheap, efficient, and secure identification and authentication of devices. In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in...
Provided by Springer Science+Business Media
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White Papers
Pulsed Multi-Layered Image Filtering: A VLSI Implementation
Jun 2009
Image convolution similar to the receptive fields found in mammalian visual pathways has long been used in conventional image processing in the form of Gabor masks. However, no VLSI implementation...
Provided by Dresden University of Technology
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White Papers
A Flexible Design Flow for Software IP Binding in Commodity FPGA
Aug 2009
SoftWare Intellectual Property (SWIP) is a critical component of increasingly complex FPGA based System On Chip (SOC) designs. As a result, developers want to ensure that their SWIP sources are...
Provided by Virginia Polytechnic Institute and State University
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White Papers
Increasing the Sensitivity of On-Chip Digital Thermal Sensors With Pre-Filtering
May 2009
Thermal monitoring has been broadly used to protect high-end integrated circuits from over-heating and to identify hot-spots in complex circuits. In this paper, the authors present a method to...
Provided by Virginia Tech
-
White Papers
Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects
Jun 2009
Hardware masking is a well-known countermeasure against Side-Channel Attacks (SCA). Like many other countermeasures, the side-channel resistance of masked circuits is susceptible to low-level...
Provided by Springer Science+Business Media
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White Papers
Physical Unclonable Function and True Random Number Generator : A Compact and Scalable Implementation
May 2009
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signatures and volatile...
Provided by Association for Computing Machinery
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White Papers
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
Jan 2009
Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integrating several soft...
Provided by Springer Science+Business Media
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White Papers
Energy and Performance Evaluation of an FPGA-Based SoC Platform With AES and PRESENT Coprocessors
Jul 2008
Hardware implementations of block ciphers have been intensively evaluated for years. The hardware profile, including the performance, area and power of a block cipher, only considers the block...
Provided by Springer Science+Business Media
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White Papers
Secure FPGA Circuits Using Controlled Placement and Routing
Oct 2007
In current Field-Programmable-LoGic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an existing circuit...
Provided by Association for Computing Machinery
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White Papers
BOOM: Broadcast Optimizations for On-Chip Meshes
Mar 2011
Future many-core chips will require an on-chip network that can support broadcasts and multicasts at good power-performance. A vanilla on-chip network would send multiple unicast packets for each...
Provided by Massachusetts Institute of Technology
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White Papers
Optimized Test Scheduling With Reduced Wrapper Cell for Embedded Core Testing
Mar 2011
The increasing Design for Test (DfT) area overhead and potential performance degradation is caused due to wrapping all the embedded cores for modular System-on-Chip (SoC) testing. This paper...
Provided by JATIT
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White Papers
An Accurate Flip-Flop Selection Technique for Reducing Logic SER
Mar 2008
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In particular, the...
Provided by University of Wisconsin-Madison
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White Papers
An Analytical Model for the Upper Bound on Temperature Differences on a Chip
May 2008
The main contribution of this work is an analytical model for finding the upper bound on the temperature difference among various locations on the die. The proposed model can be used in many...
Provided by Association for Computing Machinery
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White Papers
Temperature Management in Multiprocessor SoCs Using Online Learning
Jun 2008
In deep submicron circuits, thermal hot spots and high temperature gradients increase the cooling costs, and degrade reliability and performance. In this paper, the authors propose a low-cost...
Provided by Association for Computing Machinery
-
White Papers
Dynamic Thermal Management in 3D Multicore Architectures
Jan 2009
Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently...
Provided by UC Regents
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White Papers
Scheduling Threads for Constructive Cache Sharing on CMPs
Jun 2007
In Chip MultiProcessors (CMPs), limiting the number of off - chip cache misses is crucial for good performance. Many multithreaded programs provide opportunities for constructive cache sharing, in...
Provided by Association for Computing Machinery
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White Papers
An Analysis of Database System Performance on Chip Multiprocessors
Jul 2007
Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, high levels of...
Provided by Carnegie Mellon University
-
White Papers
An Analytical Model to Study Optimal Area Breakdown Between Cores and Caches in a Chip Multiprocessor
Mar 2009
A key design issue for Chip MultiProcessors (CMPs) is how to exploit the finite chip area to get the best system throughput. The most dominant area-consuming components in a CMP are processor...
Provided by University of Pittsburgh
-
White Papers
Level Shifter Design for Low Power Applications
Oct 2010
With the growing demand of handheld devices like cellular phones, multimedia devices, personal note books etc., low power consumption has become major design consideration for VLSI circuits and...
Provided by Guru Jambheshwar University
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White Papers
Towards the Analysis of Transactional Software
Oct 2007
The computer-architecture community's recent focus on multi-core architectures has spurred renewed interest in concurrent-programming techniques and abstractions. For programmers to take advantage...
Provided by University of Wisconsin System
-
White Papers
FPGA Based Adaptive Neuro Fuzzy Inference Controller for Full Vehicle Nonlinear Active Suspension Systems
Oct 2010
The conventional controller like the PID controller requires an exact mathematical model of the controlled system to meet as much control objectives as possible. If it is difficult to establish...
Provided by University of Sussex
-
White Papers
OpenFPGA CoreLib Core Library Interoperability Effort
Mar 2008
This paper begins by summarizing the goals of the OpenFPGA CoreLib Working Group to facilitate the interoperability of FPGA circuit cores within a variety of FPGA design tools, including...
Provided by Reed Elsevier
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White Papers
Efficient Hardware Code Generation for FPGAs
May 2008
The wider acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. The authors describe the code generation approach...
Provided by Association for Computing Machinery
-
White Papers
A Compiler Intermediate Representation for Reconfigurable Fabrics
Sep 2008
Configurable computing relies on the expression of a computation as a circuit. Its main purpose is the hardware based acceleration of programs. Configurable computing has received renewed interest...
Provided by Springer Science+Business Media
-
White Papers
Compiler Generated Systolic Arrays For wavefront Algorithm Acceleration on FPGAs
Sep 2008
Wavefront algorithms, such as the Smith-Waterman algorithm, are commonly used in bioinformatics for exact local and global sequence alignment. These algorithms are highly computationally intensive...
Provided by Sandbridge Technologies
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White Papers
Compiled Hardware Acceleration of Molecular Dynamics Code
Sep 2008
The objective of Molecular Dynamics (MD) simulations is to determine the shape of a molecule in a given biomolecular environment. These simulations are very demanding computationally, where...
Provided by University of California
-
White Papers
Accelerating Dynamic Time Warping Subsequence Search With GPUs and FPGAs
Dec 2010
Many time series data mining problems require subsequence similarity search as a subroutine. Dozens of similarity/distance measures have been proposed in the last decade and there is increasing...
Provided by University of California
-
White Papers
Designing Modular Hardware Accelerators in C With ROCCC 2.0
May 2010
While FPGA-based hardware accelerators have repeatedly been demonstrated as a viable option, their programmability remains a major barrier to their wider acceptance by application code developers....
Provided by University of California
-
White Papers
On Self-Timed Circuits in Real-Time Systems
Jan 2011
While asynchronous logic has many potential advantages compared to traditional synchronous designs, one of the major drawbacks is its unpredictability with respect to temporal behavior. Having no...
Provided by Hindawi Publishing
-
White Papers
An FPGA-Based Adaptable 200 MHz Bandwidth Channel Sounder for Wireless Communication Channel Characterisation
Jan 2011
This paper describes the development of a fast adaptable FPGA-based wide-band channel sounder with signal bandwidths of up to 200MHz and channel sampling rates up to 5.4 kHz. The application of...
Provided by Hindawi Publishing
-
White Papers
The Potential for a GPU-Like Overlay Architecture for FPGAs
Dec 2010
The authors propose a soft processor programming model and architecture inspired by Graphics Processing Units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and...
Provided by Hindawi Publishing
-
White Papers
An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads
Dec 2010
Parallel graph-oriented applications expressed in the Bulk-Synchronous Parallel (BSP) and Token Dataflow compute models generate highly-structured communication workloads from messages propagating...
Provided by Hindawi Publishing
-
White Papers
Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates
Dec 2010
The aggressive scaling of CMOS technology has increased the density and allowed the integration of multiple processors into a single chip. Although solutions based on MPSoC architectures can...
Provided by Hindawi Publishing
-
White Papers
Floorplacement for Partial Reconfigurable FPGA-Based Systems
Dec 2010
The authors presented a resource- and configuration-aware floor-placement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength. Their work...
Provided by Hindawi Publishing
-
White Papers
High-Level Synthesis of In-Circuit Assertions for Verification
Dec 2010
Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-Level Synthesis (HLS) tools have...
Provided by Hindawi Publishing
-
White Papers
FPGA Implementation for GMM-Based Speaker Identification
Nov 2010
In today's society, highly accurate personal identification systems are required. Passwords or pin numbers can be forgotten or forged and are no longer considered to offer a high level of...
Provided by Hindawi Publishing
-
White Papers
An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms
Nov 2010
The design of complex circuits as SoCs presents two great challenges to designers. One is the speeding up of system functionality modeling and the second is the implementation of the system in an...
Provided by Hindawi Publishing
-
White Papers
A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos
Oct 2010
This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation that targets high-definition videos. This design can process very high-definition videos...
Provided by Hindawi Publishing
-
White Papers
FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition
Sep 2010
A scalable large vocabulary, speaker independent speech recognition system is being developed using Hidden Markov Models (HMMs) for acoustic modeling and a Weighted Finite State Transducer (WFST)...
Provided by Hindawi Publishing
-
White Papers
Low-Complexity Online Synthesis for AMIDAR Processors
Dec 2010
Future chip technologies will change the way the authors deal with hardware design. First of all, logic resources will be available in vast amount. Furthermore, engineering specialized designs for...
Provided by Hindawi Publishing
-
White Papers
Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures
Dec 2010
Field-Programmable Gate Arrays (FPGAs) and other Reconfigurable Computing (RC) devices have been widely shown to have numerous advantages including order of magnitude performance and power...
Provided by Hindawi Publishing
-
White Papers
Reconfigurable Multiprocessor Systems: A Review
Oct 2010
Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them. This approach provides better results in terms of area, speed, and...
Provided by Hindawi Publishing
-
White Papers
Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic
Nov 2010
Dynamic Partial Reconfiguration (DPR) allows one to adapt hardware resources to meet time-varying requirements in power, resources, or performance. In this paper, the authors present two new DPR...
Provided by Hindawi Publishing
-
White Papers
Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics
Oct 2010
FPGA design of side-channel analysis countermeasures using unmasked dual-rail with pre-charge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful...
Provided by Hindawi Publishing
-
White Papers
Mechanism of Resource Virtualization in RCS for Multitask Stream Applications
Sep 2010
Virtualization of logic, routing, and communication resources in recent FPGA devices can provide a dramatic improvement in cost-efficiency for Reconfigurable Computing systems (RCSs). The...
Provided by Hindawi Publishing
-
White Papers
3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans
Aug 2010
The authors propose new 3D 2-layer and 3-layer NoC architectures that utilize homogeneous regular mesh networks on a separate layer and one or two heterogeneous floorplanning layers. These...
Provided by Hindawi Publishing
-
White Papers
Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing
Jun 2010
This paper presents the design of a reconfigurable asynchronous computing element, called the Pulsed Quad-cell (PQ-cell), for constructing conformal computers. Conformal computers are systems with...
Provided by Hindawi Publishing
-
White Papers
New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA
Apr 2010
Currently, reconfigurable hardware devices feature a high density of heterogeneous resources to enable multitasking and offer flexibility in application needs. These concepts raise the need for...
Provided by Hindawi Publishing
-
White Papers
Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study
Feb 2010
Reconfigurable Computers (RCs) are traditional computers extended with co-processors based on reconfigurable hardware like FPGAs. Representative RC systems include SGI RC100, SRC-6, and Cray XD1....
Provided by Hindawi Publishing
-
White Papers
Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs
Jan 2010
The authors present a method for implementing high speed Finite Impulse Response (FIR) filters on Field Programmable Gate Arrays (FPGAs). Their algorithm is a multiplierless technique where fixed...
Provided by Hindawi Publishing
-
White Papers
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures
Nov 2009
The dynamic and partial reconfiguration of FPGAs enables the dynamic placement in reconfigurable zones of the tasks that describe an application. However, the dynamic management of the tasks...
Provided by Hindawi Publishing
-
White Papers
Power Characterisation for Fine-Grain Reconfigurable Fabrics
Oct 2009
This paper proposes a benchmarking methodology for characterising the power consumption of the fine-grain fabric in reconfigurable architectures. This methodology is part of the GroundHog 2009...
Provided by Hindawi Publishing
-
White Papers
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms
Dec 2009
This paper presents the OveRSoC project. The objective is to develop an exploration and validation methodology of embedded Real Time Operating Systems (RTOSs) for Reconfigurable...
Provided by Hindawi Publishing
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White Papers
An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures
Sep 2009
This paper proposes an exact ILP formulation for the task scheduling problem on a 2D dynamically and partially reconfigurable architecture. The authors' approach takes physical constraints of the...
Provided by Hindawi Publishing
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White Papers
A Hardware Filesystem Implementation with Multidisk Support
Aug 2009
Modern High-End Computing systems frequently include FPGAs as compute accelerators. These programmable logic devices now support disk controller IP cores which offer the ability to introduce new,...
Provided by Hindawi Publishing
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White Papers
FPGA Interconnect Topologies Exploration
Jul 2009
This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest...
Provided by Hindawi Publishing
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White Papers
Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings
Jun 2009
A True Random Number Generator (TRNG) is an important component in cryptographic systems. Designing a fast and secure TRNG in an FPGA is a challenging task. In this paper, the authors analyze the...
Provided by Hindawi Publishing
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White Papers
A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips
May 2009
The authors present a heuristic algorithm for the run-time distribution of task sets in a homogeneous Multiprocessor network-on-chip. The algorithm is itself distributed over the processors and...
Provided by Hindawi Publishing
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White Papers
A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation
May 2009
Channel estimation in wireless communication systems is usually accomplished by inserting, along with the information, a series of known symbols, whose analysis is used to define the parameters of...
Provided by Hindawi Publishing
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White Papers
An Adaptive Message Passing MPSoC Framework
Apr 2009
Multi-Processor Systems-on-Chips (MPSoCs) offer superior performance while maintaining flexibility and reusability thanks to software oriented personalization. While most MPSoCs are today...
Provided by Hindawi Publishing
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White Papers
A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime
May 2009
Run-time reconfigurable system-on-chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying...
Provided by Hindawi Publishing
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White Papers
Multilevel Simulation of Heterogeneous Reconfigurable Platforms
Apr 2009
This paper presents a general system-level simulation and testing methodology for reconfigurable System-on-Chips, starting from behavioral specifications of system activities to multilevel...
Provided by Hindawi Publishing
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White Papers
A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks
Apr 2009
FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs) applications, offering the key requirement of reconfigurability. However,...
Provided by Hindawi Publishing
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White Papers
High level modeling of Dynamic Reconfigurable FPGAs
Mar 2009
As System-on-Chip (SoC) based embedded systems have become a defacto industry standard, their overall design complexity has increased exponentially in recent years, necessitating the introduction...
Provided by Hindawi Publishing
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White Papers
Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs
Jan 2009
Modern FPGAs contain embedded DSP blocks, which can be configured as multipliers with more than one possible size. FPGA-based designs using these multigranular embedded blocks become more...
Provided by Hindawi Publishing
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White Papers
The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units
Oct 2008
This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and...
Provided by Hindawi Publishing
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White Papers
Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration
Nov 2008
In real-time signal processing, a single application often has multiple computationally intensive kernels that can benefit from acceleration using custom or reconfigurable hardware platforms, such...
Provided by Hindawi Publishing
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White Papers
Burst-Mode Asynchronous Controllers on FPGA
Oct 2008
FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. The authors propose a method...
Provided by Hindawi Publishing
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