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asics - chip sets
(383 results)-
White Papers
Enhanced Core Processor Blocks of OFDM System
Sep 2011
OFDM is a multi carrier modulation technique in which the carriers are Orthogonal to each others as a result of which it provides high bandwidth efficiency and multiple carriers share the data...
Provided by International Journal of Electronics Communication and Computer Engineering
-
White Papers
A Software-Supported Methodology for Designing General-Purpose Interconnection Networks for Reconfigurable Architectures
Jan 2012
Modern applications realized onto FPGAs exhibit high connectivity demands. Throughout this paper, the authors study the routing constraints of Virtex devices and they propose a systematic...
Provided by Democritus University of Thrace
-
White Papers
CAD Tools for Designing 3D Integrated Systems
Jun 2011
Expectations of consumer for future consumer electronics devices put significant strain on conventional design and manufacturing processes. Integrating more functionality in a smaller form factor...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Novel Methodology for Architecture-Level Exploration of 3D SoCs
May 2011
Three-Dimensional (3D) integration is an emerging technology that is expected to lead to tremendous benefits in terms of power, delay and silicon area. Moreover, 3D technology continues...
Provided by National Technical University of Athens
-
White Papers
A Software-Supported Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs
Jan 2009
Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencies and logic...
Provided by National Technical University of Athens
-
White Papers
System-Level Exploration of 3-D Interconnection Schemes
Nov 2008
3-D chip stacking is the big next step in system integration. Even though the process technology is maturing, many issues related to system implementation are not fully understood yet....
Provided by National Technical University of Athens
-
White Papers
A Novel Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs
Dec 2008
In current reconfigurable architectures the interconnection structures increasingly contribute more to the delay and power consumption. The demand for increased clock frequencies and logic density...
Provided by National Technical University of Athens
-
White Papers
Three Dimensional FPGA Architectures: A Shift Paradigm for Energy-Performance Efficient DSP Implementations
Jan 2012
Modern applications exhibit increased complexity which introduces extra constraints during implementation related to delay, power consumption and silicon area. This problem is even more important...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Software-Supported Methodology for Designing High-Performance 3D FPGA Architectures
Dec 2007
A software-supported systematic methodology for exploring and evaluating alternative 3D reconfigurable FPGA architectures is introduced. Two new software tools were developed: a placement and...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support
Aug 2007
This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: the 3DPRO for placement and routing on 3D FPGAs and the...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Fault-Free: A Framework for Supporting Fault Tolerance in FPGAs
Nov 2009
In this paper, the authors propose a novel methodology for supporting application mapping onto FPGAs with fault tolerance even if this feature is not supported by the target platform. For the...
Provided by National Technical University of Athens
-
White Papers
Towards Supporting Fault-Tolerance in FPGAs
Apr 2010
This paper proposes a novel methodology for improving reliability of FPGAs without requiring special purpose hardware. In contrast to related approaches that are applied uniformly over the target...
Provided by National Technical University of Athens
-
White Papers
A Framework for Enabling Fault Tolerance in Reconfigurable Architectures
Dec 2009
Fault tolerance is a pre-request not only for safety critical systems, but almost for the majority of applications. However, the additional hardware elements impose performance degradation. In...
Provided by National Technical University of Athens
-
White Papers
Trading Fault-Masking With Performance Overhead for FPGAs
Jan 2011
Reliability issues become an important design concern with technology scaling. This paper introduces a novel methodology for balancing the desired fault masking and the consequence delay and power...
Provided by National Technical University of Athens
-
White Papers
Thermal Optimization for Micro-Architectures Through Selective Block Replication
May 2011
Increased power densities result to higher on-chip temperatures, which in turn creates numerous problems tightly firmed to reliability issues. This problem is expected to become even more severe...
Provided by National Technical University of Athens
-
White Papers
Quick Hotspot: A Software Supported Methodology for Supporting Run-Time Thermal Analysis at MPSoC Designs
Jan 2011
Detailed thermal analysis and exploration has recently received significant attention since it is straightforward-related to numerous reliability issues. Furthermore, thermal profiling is a...
Provided by National Technical University of Athens
-
White Papers
A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs
Dec 2010
This paper introduces a novel methodology for enabling rapid exploration of memory hierarchies onto FPGA devices. The methodology is software supported by a new open-source tool framework, named...
Provided by National Technical University of Athens
-
White Papers
Hierarchical Segmentation for Hardware Function Evaluation
Dec 2008
This paper presents a method for evaluating functions based on piecewise polynomial approximations (splines) with a hierarchical segmentation scheme targeting hardware implementation. The...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration
Jun 2011
A present-day System-on-Chip (SoC) runs a wide range of applications with diverse real-time requirements. Resources, such as processors, interconnects and memories, are shared between these...
Provided by Eindhoven University of Technology (TU/e)
-
White Papers
Modeling Reconfiguration in a FPGA With a Hardwired Network on Chip
Feb 2009
The authors propose that FPGAs use a HardWired Network On Chip (HWNOC) as a unified interconnect for functional communications (data and control) as well as configuration (bitstreams for soft IP)....
Provided by Delft University of Technology
-
White Papers
Performance Analysis of Soft and Hard Single-Hop and Multi-Hop Circuit-Switched Interconnects for FPGAs
Jul 2008
This paper presents a performance analysis of hard and soft on-chip networks for FPGAs. The authors applied the Jackson's queuing model to analyze the performance of a MultiProcessor System on a...
Provided by Delft University of Technology
-
White Papers
Hardwired Networks on Chip in FPGAs to Unify Functional and Configuration Interconnects
Jan 2008
The authors propose that Networks on Chip (NOC) are hard-wired in Field-Programmable Gate Arrays (FPGA). Although some area of the FPGA then has a fixed function, this loss of flexibility is...
Provided by Delft University of Technology
-
White Papers
Configurable M-Factor VLSI DVB-S2 LDPC Decoder Architecture With Optimized Memory Tiling Design
Mar 2012
Semi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but...
Provided by EURASIP
-
White Papers
Random Number Generation Based on Oscillatory Metastability in Ring Circuits
Nov 2011
Random number generator designs are discussed, which utilize oscillatory metastability, induced by switching between two stable states of ring-connected digital gates. For a short time after the...
Provided by International Association for Cryptologic Research
-
White Papers
Groestl Tweaks and Their Effect on FPGA Results
Nov 2011
The authors have performed the first order analysis of the influence of the Round 3 tweaks in Groestl on the performance of this algorithm in FPGAs. Both Groestl-0 and the revised Groestl have...
Provided by George Mason University
-
White Papers
Analog Integrated Circuit Design and Testing Using the Field Programmable Analog Array Technology
Sep 2011
Due to their reliability, performance and rapid prototyping, programmable logic devices overcome the use of ASICs in the digital system design. However, the similar solution for analog signals was...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
-
White Papers
Efficient Implementations of Discrete Wavelet Transforms Using FPGAs
Sep 2011
Recently, the Wavelet Transform has gained a lot of popularity in the field of signal and image processing. This is due to its capability of providing both time and frequency information...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
-
White Papers
LFSR Test Pattern for Fault Detection and Diagnosis for FPGA CLB Cells
Mar 2012
The increasing growth of sub-micron technology has resulted in the difficulty of VLSI testing. Test and design for testability are recognized today as critical to a successful design. Field...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
-
White Papers
VLSI Implementation of Fast Convolution Based 2-D Discrete Wavelet Transform for High Speed, Area Efficient Image Computing
Mar 2012
A VLSI design approach of a high speed and real-time 2-D Discrete Wavelet Transform computing is being presented in the paper. The proposed architecture, based on new and fast convolution...
Provided by International Journal of Power Control Signal and Computation (IJPCSC)
-
White Papers
Implementation of Area Efficient Memory-Based FIR Digital Filter Using LUT-Multiplier
Mar 2012
Memory based structures are well-suited for many Digital Signal Processing (DSP) applications, which involve multiplication with a fixed set of coefficients. Memory-based structures are more...
Provided by International Journal of Computer Science and Information Technologies
-
White Papers
Integrating Logic Analyzer Functionality Into VHDL Designs
Jan 2012
A combined hardware and software system for the debugging of FPGA designs is designed. It provides a powerful logic analyzer implemented as a fully parameterized VHDL description. The system can...
Provided by International Journal of Computer Science and Information Technologies
-
White Papers
High Speed and Low Power Dynamic Latched Comparator for PTL Circuit Applications
Jan 2012
Comparators are basic building blocks for designing modern mixed signal systems. Speed and resolution are two important factors which are required for high speed applications. This paper presents...
Provided by International Journal of Computer Science and Information Technologies
-
White Papers
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits With Clock Networks
Jun 2011
Analyzing timing yield under process variations is difficult because of the presence of correlations. Reconvergent Fan-Out Nodes (RFONs) within combinational subcircuits are a major source of...
Provided by World Scientific Publishing
-
White Papers
CTC: An End-to-End Flow Control Protocol for Multi-Core Systems-on-Chip
May 2009
The authors propose Connection Then Credits (CTC) as a new end-to-end flow control protocol to handle message-dependent deadlocks in Networks-on-Chip (NoC) for multi-core systems-on-chip. CTC is...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Distributed Flit-Buffer Flow Control for Networks-on-Chip
Oct 2008
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for Networks-on-Chip (NoC). Since they both rely on backpressure, the two techniques...
Provided by Association for Computing Machinery
-
White Papers
A Methodology for Constraint-Driven Synthesis of On-Chip Communications
Mar 2009
The authors present a methodology and an optimization framework for the synthesis of on-chip communication through the assembly of components such as interfaces, routers, buses and links, from a...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
FPGA Real Time Acceleration for Discrete Wavelet Transform of the 5/3 Filter for JPEG2000 Standard
Mar 2012
In recent years video and image compression have became very required. The availability of powerful software design tools is a fundamental requirement to take advantage of the many advanced and...
Provided by Academy & Industry Research Collaboration Center
-
White Papers
Design and Optimization of Full Comparator Based on Quantum-Dot Cellular Automata
Apr 2012
Quantum-dot Cellular Automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power...
Provided by ETRI Journal
-
White Papers
CTC Turbo Decoding Architecture for LTE Systems Implemented on FPGA
Feb 2012
This paper describes a turbo decoder for Long Term Evolution (LTE) standard, release 8, using a Max Log MAP algorithm. The Forward Error Correction (FEC) block dimensions, as indicated in the...
Provided by IARIA
-
White Papers
A Tool for Signal Probability Analysis of FPGA-Based Systems
Sep 2011
The authors describe a model of Field Programmable Gate Array based systems realised with the Stochastic Activity Networks formalism. The model can be used to debug the circuit design synthesised...
Provided by IARIA
-
White Papers
A Flexible Architecture for Fisheye Correction in Automotive Rear-View Cameras
Oct 2008
Fisheye cameras are finding an increasing number of applications in automobile rear-view imaging systems due to their ultra-wide-angle properties and cost-effectiveness. However, while fisheye...
Provided by Altera
-
White Papers
Voltage Regulator Selection for FPGAs
Nov 2008
As FPGAs increase in sophistication to provide additional features such as Phase-Locked Loops (PLLs), memory interfaces, and transceiver functionality, the power requirements and designs for FPGAs...
Provided by Altera
-
White Papers
FPGAs Enable Energy-Efficient Motor Control in Next-Generation Smart Home Appliances
Nov 2008
Home appliances are at the heart of the modern lifestyle. Consumers want them "Smart," "Green," and, of course, always cheaper. All those diverging requirements have pushed today's home-appliance...
Provided by Altera
-
White Papers
40-nm FPGAs: Architecture and Performance Comparison
Dec 2008
FPGA users are constantly looking for ways to differentiate their products in the market place and in doing so they define new systems with new requirements. The new requirements usually are...
Provided by Altera
-
White Papers
40-nm FPGA Power Management and Advantages
Dec 2008
The 40-nm process offers clear benefits over prior nodes, including the 65-nm node and the more recent 45-nm node. One of the most attractive benefits is higher integration, which enables...
Provided by Altera
-
White Papers
Image-Based Driver Assistance Development Environment
Dec 2008
This white paper describes a development environment for all Driver Assistance (DA) requirements using Altera FPGA and HardCopy ASIC devices. This development environment consists of a development...
Provided by Altera
-
White Papers
Selecting the Ideal FPGA Vendor for Military Programs
Feb 2009
Developing a system design for government projects typically requires a defense contractor to evaluate and make system decisions based on documents such as a Request For Proposal (RFP), Statement...
Provided by Altera
-
White Papers
Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints
Feb 2009
Electronic systems designers use FPGAs for their prototype implementations, taking advantage of the devices' reprogrammability to validate hardware and software. Once the design is ready for...
Provided by Altera
-
White Papers
Video Processing on FPGAs for Military Electro-Optical/Infrared Applications
Mar 2009
Many of today's Electro-Optical/Infrared (EO/IR) systems require high-complexity, real-time video processing within a constrained power budget. The latest low-power, low-cost FPGA families - with...
Provided by Altera
-
White Papers
Simplifying Simultaneous Multimode RRH Design
Mar 2009
RRH technology with support for simultaneous operation of multiple air-interface protocols is an emerging end-product requirement. The diverse modulation formats and sampling rates between...
Provided by Altera
-
White Papers
Avoiding PCB Design Mistakes in FPGA-Based Systems
Mar 2009
System design using FPGAs is significantly different from the regular ASIC and processor-based system design. This white paper will examine some of the contributing factors, and more importantly,...
Provided by Altera
-
White Papers
Automating DSP Simulation and Implementation of Military Sensor Systems
Mar 2009
Military sensor-driven systems normally use FPGAs to interface with the Analog to Digital Converters (ADCs) that digitize sensor inputs. The ADCs operate at rates of up to 3 MSPS, which requires...
Provided by Altera
-
White Papers
Using FPGAs to Render Graphics and Drive LCD Interfaces
Apr 2009
This paper describes the use of FPGAs to add a LCD and GUI display to any embedded system. Unlike fixed processor device implementations, this approach is scalable and can support any display...
Provided by Altera
-
White Papers
FPGAs at 40 nm and >10 Gbps: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers
Apr 2009
This paper describes key technologies that enable Stratix IV GT FPGAs to deliver the performance and capabilities necessary to support 40G/100G applications with integrated 11.3-Gbps transceivers....
Provided by Altera
-
White Papers
Generating Panoramic Views by Stitching Multiple Fisheye Images
May 2009
Fisheye cameras are finding an increasing number of applications in automobile imaging systems due to their ultra-wide-angle properties and cost-effectiveness. One such application renders a...
Provided by Altera
-
White Papers
FPGA Coprocessing Evolution: Sustained Performance Approaches Peak Performance
Jun 2009
FPGA architecture allows for many algorithm implementations where the sustained performance is much closer to the device's peak performance when compared to quad-core CPUs or GPGPUs. The strong...
Provided by Altera
-
White Papers
Protecting the FPGA Design From Common Threats
Jun 2009
The global estimated loss to counterfeiting is expected to exceed U.S.$1.5 trillion in 2009. Counterfeiting impacts all businesses in all markets, from Gucci handbags to computer chips to...
Provided by Altera
-
White Papers
Enabling Design Separation for High-Reliability and Information-Assurance Systems
Jun 2009
FPGAs are an ubiquitous part of today's processing technology. Their use has grown from traditional glue logic interfaces of the past to the most advanced information-processing systems used by...
Provided by Altera
-
White Papers
Understanding Metastability in FPGAs
Jul 2009
Metastability is a phenomenon that can cause system failure in digital devices, including FPGAs, when a signal is transferred between circuitry in unrelated or asynchronous clock domains. This...
Provided by Altera
-
White Papers
Six Ways to Replace a Microcontroller With a CPLD
Jul 2009
This white paper discusses when it is advantageous to use a CPLD instead of a microcontroller, and when a CPLD makes a good companion to a microcontroller. The examples given in this white paper...
Provided by Altera
-
White Papers
Reduce Total System Cost in Portable Applications Using Zero-Power CPLDs
Jul 2009
Traditionally, portable system designers have used ASICs and ASSPs to implement memory interfaces, I/O expansion, power-on sequencing, discrete logic functions, display, and other functions in...
Provided by Altera
-
White Papers
Implementing a Cost-Effective Human-Machine Interface for Home Appliances
Jul 2009
Traditionally, Human-Machine Interfaces (HMIs) for home appliances have been composed of mechanical devices such as buttons and knobs, coupled with display indicators such as Light-Emitting Diodes...
Provided by Altera
-
White Papers
MAX Series Configuration Controller Using Flash Memory
Sep 2009
Configuration bitstream sizes are increasing with the introduction of higher-density FPGAs. This increase requires larger configuration devices to store the data and configure these FPGAs. As an...
Provided by Altera
-
White Papers
Using LEDs as Light-Level Sensors and Emitters
Oct 2009
Modulating LED power based on ambient light level increases battery life, a particularly helpful feature in a device where battery life is measured in days. Using a very simple circuit, Altera's...
Provided by Altera
-
White Papers
Leveraging Cost-Optimized FPGAs to Deliver OTN Mapper Solutions
Oct 2009
In telecommunications transport infrastructure, Optical Transport Network (OTN) and Gigabit Ethernet (GbE) protocols are being combined to create Packet-Optical Transport Networks (P-OTNs)....
Provided by Altera
-
White Papers
High-Definition Video Deinterlacing Using FPGAs
Oct 2009
Deinterlacing was developed to address a legacy problem: the interlaced video that was required by old analog televisions must be converted to be shown on today's digital televisions. An...
Provided by Altera
-
White Papers
Taking Advantage of Advances in FPGA Floating-Point IP Cores
Oct 2009
Recently available FPGA design tools and IP provide a substantial reduction in computational resources, as well as greatly easing the implementation effort in a floating-point datapath. Moreover,...
Provided by Altera
-
White Papers
Decrease Total System Costs with Industry's Lowest Cost, Lowest Power FPGAs
Nov 2009
Corporate objectives, such as increasing profits and sales revenue while utilizing R&D efficiently, are putting severe pressure on today's design engineering teams. The resulting system level...
Provided by Altera
-
White Papers
Supporting Digital Television Trends With Next-Generation FPGAs
Feb 2010
The proliferation of so many different digital television models-better known as market fragmentation- and differing regional market requirements, combined with the desire to add new features and...
Provided by Altera
-
White Papers
Using 10-Gbps Transceivers in 40G/100G Applications
Feb 2010
This white paper identifies the key drivers behind the migration to 100G interfaces, and shows how to leverage the unique ability of FPGAs to implement this high-speed interface. The emerging...
Provided by Altera
-
White Papers
Developing Functional Safety Systems With TÜV-Qualified FPGAs
Mar 2010
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA...
Provided by Altera
-
White Papers
Driving Flexibility Into Automotive Electronics Design
Mar 2010
With the dramatic increase in development costs for state-of-the-art process technologies, such as next-generation automotive electronic systems, specialization of traditional microcontrollers no...
Provided by Altera
-
White Papers
Enabling Improved Image Format Conversion With FPGAs
Apr 2010
Broadcast infrastructure systems - such as servers, switchers, head-end encoders, and specialty studio displays - support a multitude of input image formats, and commonly require images to be...
Provided by Altera
-
White Papers
Extending Transceiver Leadership at 28 nm
May 2010
High-speed serial protocols with increased data rates and expanded capabilities are addressing the demand for more network bandwidth. Efficiently supporting the subsequent increase in system...
Provided by Altera
-
White Papers
Enabling High-Precision DSP Applications With the FPGA Industry's First Variable-Precision Architecture
May 2010
The silicon Digital Signal Processing (DSP) architecture of the FPGA can make a big difference when implementing complex signal-processing algorithms. Altera's Stratix V FPGAs, with the...
Provided by Altera
-
White Papers
Enabling Low-Power EO/IR System Development With FPGAs and Image- and Sensor-Processing IP
Jun 2010
Before embarking on the development of a next-generation Electro-Optical and Infrared (EO/IR) system, it is important to not only understand the power and performance characteristics of the FPGA,...
Provided by Altera
-
White Papers
Boosting System Performance With External Memory Solutions
Jun 2010
Over 70% of designs on Altera FPGAs require some type of external memory in the design, but the needs vary depending on the individual application. This white paper addresses all aspects of...
Provided by Altera
-
White Papers
Building an IP Surveillance Camera System With a Low-Cost FPGA
Jun 2010
In the video surveillance marketplace, the need for higher quality video, higher resolution, and more flexibility and features is driving the change from analog to digital cameras. By definition,...
Provided by Altera
-
White Papers
Accelerating DSP Designs With the Total 28-nm DSP Portfolio
Jul 2010
Implementing Digital Signal Processing (DSP) datapaths with different performance, precision, Intellectual Property (IP), and development flows is challenging and labor-intensive. As more and more...
Provided by Altera
-
White Papers
Understanding 40-nm FPGA Solutions for SATA/SAS
Jul 2010
Serial ATA (SATA) and Serial Attached SCSI (SAS) are computer bus standards that have the primary function of transferring data (directly or otherwise) between the motherboard and mass storage...
Provided by Altera
-
White Papers
Enhanced Core Processor Blocks of OFDM System
Sep 2011
OFDM is a multi carrier modulation technique in which the carriers are Orthogonal to each others as a result of which it provides high bandwidth efficiency and multiple carriers share the data...
Provided by International Journal of Electronics Communication and Computer Engineering
-
White Papers
A Software-Supported Methodology for Designing General-Purpose Interconnection Networks for Reconfigurable Architectures
Jan 2012
Modern applications realized onto FPGAs exhibit high connectivity demands. Throughout this paper, the authors study the routing constraints of Virtex devices and they propose a systematic...
Provided by Democritus University of Thrace
-
White Papers
CAD Tools for Designing 3D Integrated Systems
Jun 2011
Expectations of consumer for future consumer electronics devices put significant strain on conventional design and manufacturing processes. Integrating more functionality in a smaller form factor...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Novel Methodology for Architecture-Level Exploration of 3D SoCs
May 2011
Three-Dimensional (3D) integration is an emerging technology that is expected to lead to tremendous benefits in terms of power, delay and silicon area. Moreover, 3D technology continues...
Provided by National Technical University of Athens
-
White Papers
A Software-Supported Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs
Jan 2009
Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencies and logic...
Provided by National Technical University of Athens
-
White Papers
System-Level Exploration of 3-D Interconnection Schemes
Nov 2008
3-D chip stacking is the big next step in system integration. Even though the process technology is maturing, many issues related to system implementation are not fully understood yet....
Provided by National Technical University of Athens
-
White Papers
A Novel Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs
Dec 2008
In current reconfigurable architectures the interconnection structures increasingly contribute more to the delay and power consumption. The demand for increased clock frequencies and logic density...
Provided by National Technical University of Athens
-
White Papers
Three Dimensional FPGA Architectures: A Shift Paradigm for Energy-Performance Efficient DSP Implementations
Jan 2012
Modern applications exhibit increased complexity which introduces extra constraints during implementation related to delay, power consumption and silicon area. This problem is even more important...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Software-Supported Methodology for Designing High-Performance 3D FPGA Architectures
Dec 2007
A software-supported systematic methodology for exploring and evaluating alternative 3D reconfigurable FPGA architectures is introduced. Two new software tools were developed: a placement and...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support
Aug 2007
This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: the 3DPRO for placement and routing on 3D FPGAs and the...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Fault-Free: A Framework for Supporting Fault Tolerance in FPGAs
Nov 2009
In this paper, the authors propose a novel methodology for supporting application mapping onto FPGAs with fault tolerance even if this feature is not supported by the target platform. For the...
Provided by National Technical University of Athens
-
White Papers
Towards Supporting Fault-Tolerance in FPGAs
Apr 2010
This paper proposes a novel methodology for improving reliability of FPGAs without requiring special purpose hardware. In contrast to related approaches that are applied uniformly over the target...
Provided by National Technical University of Athens
-
White Papers
A Framework for Enabling Fault Tolerance in Reconfigurable Architectures
Dec 2009
Fault tolerance is a pre-request not only for safety critical systems, but almost for the majority of applications. However, the additional hardware elements impose performance degradation. In...
Provided by National Technical University of Athens
-
White Papers
Trading Fault-Masking With Performance Overhead for FPGAs
Jan 2011
Reliability issues become an important design concern with technology scaling. This paper introduces a novel methodology for balancing the desired fault masking and the consequence delay and power...
Provided by National Technical University of Athens
-
White Papers
Thermal Optimization for Micro-Architectures Through Selective Block Replication
May 2011
Increased power densities result to higher on-chip temperatures, which in turn creates numerous problems tightly firmed to reliability issues. This problem is expected to become even more severe...
Provided by National Technical University of Athens
-
White Papers
Quick Hotspot: A Software Supported Methodology for Supporting Run-Time Thermal Analysis at MPSoC Designs
Jan 2011
Detailed thermal analysis and exploration has recently received significant attention since it is straightforward-related to numerous reliability issues. Furthermore, thermal profiling is a...
Provided by National Technical University of Athens
-
White Papers
A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs
Dec 2010
This paper introduces a novel methodology for enabling rapid exploration of memory hierarchies onto FPGA devices. The methodology is software supported by a new open-source tool framework, named...
Provided by National Technical University of Athens
-
White Papers
Hierarchical Segmentation for Hardware Function Evaluation
Dec 2008
This paper presents a method for evaluating functions based on piecewise polynomial approximations (splines) with a hierarchical segmentation scheme targeting hardware implementation. The...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration
Jun 2011
A present-day System-on-Chip (SoC) runs a wide range of applications with diverse real-time requirements. Resources, such as processors, interconnects and memories, are shared between these...
Provided by Eindhoven University of Technology (TU/e)
-
White Papers
Modeling Reconfiguration in a FPGA With a Hardwired Network on Chip
Feb 2009
The authors propose that FPGAs use a HardWired Network On Chip (HWNOC) as a unified interconnect for functional communications (data and control) as well as configuration (bitstreams for soft IP)....
Provided by Delft University of Technology
-
White Papers
Performance Analysis of Soft and Hard Single-Hop and Multi-Hop Circuit-Switched Interconnects for FPGAs
Jul 2008
This paper presents a performance analysis of hard and soft on-chip networks for FPGAs. The authors applied the Jackson's queuing model to analyze the performance of a MultiProcessor System on a...
Provided by Delft University of Technology
-
White Papers
Hardwired Networks on Chip in FPGAs to Unify Functional and Configuration Interconnects
Jan 2008
The authors propose that Networks on Chip (NOC) are hard-wired in Field-Programmable Gate Arrays (FPGA). Although some area of the FPGA then has a fixed function, this loss of flexibility is...
Provided by Delft University of Technology
-
White Papers
Configurable M-Factor VLSI DVB-S2 LDPC Decoder Architecture With Optimized Memory Tiling Design
Mar 2012
Semi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but...
Provided by EURASIP
-
White Papers
Random Number Generation Based on Oscillatory Metastability in Ring Circuits
Nov 2011
Random number generator designs are discussed, which utilize oscillatory metastability, induced by switching between two stable states of ring-connected digital gates. For a short time after the...
Provided by International Association for Cryptologic Research
-
White Papers
Groestl Tweaks and Their Effect on FPGA Results
Nov 2011
The authors have performed the first order analysis of the influence of the Round 3 tweaks in Groestl on the performance of this algorithm in FPGAs. Both Groestl-0 and the revised Groestl have...
Provided by George Mason University
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White Papers
Analog Integrated Circuit Design and Testing Using the Field Programmable Analog Array Technology
Sep 2011
Due to their reliability, performance and rapid prototyping, programmable logic devices overcome the use of ASICs in the digital system design. However, the similar solution for analog signals was...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Efficient Implementations of Discrete Wavelet Transforms Using FPGAs
Sep 2011
Recently, the Wavelet Transform has gained a lot of popularity in the field of signal and image processing. This is due to its capability of providing both time and frequency information...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
LFSR Test Pattern for Fault Detection and Diagnosis for FPGA CLB Cells
Mar 2012
The increasing growth of sub-micron technology has resulted in the difficulty of VLSI testing. Test and design for testability are recognized today as critical to a successful design. Field...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
VLSI Implementation of Fast Convolution Based 2-D Discrete Wavelet Transform for High Speed, Area Efficient Image Computing
Mar 2012
A VLSI design approach of a high speed and real-time 2-D Discrete Wavelet Transform computing is being presented in the paper. The proposed architecture, based on new and fast convolution...
Provided by International Journal of Power Control Signal and Computation (IJPCSC)
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White Papers
Implementation of Area Efficient Memory-Based FIR Digital Filter Using LUT-Multiplier
Mar 2012
Memory based structures are well-suited for many Digital Signal Processing (DSP) applications, which involve multiplication with a fixed set of coefficients. Memory-based structures are more...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
Integrating Logic Analyzer Functionality Into VHDL Designs
Jan 2012
A combined hardware and software system for the debugging of FPGA designs is designed. It provides a powerful logic analyzer implemented as a fully parameterized VHDL description. The system can...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
High Speed and Low Power Dynamic Latched Comparator for PTL Circuit Applications
Jan 2012
Comparators are basic building blocks for designing modern mixed signal systems. Speed and resolution are two important factors which are required for high speed applications. This paper presents...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits With Clock Networks
Jun 2011
Analyzing timing yield under process variations is difficult because of the presence of correlations. Reconvergent Fan-Out Nodes (RFONs) within combinational subcircuits are a major source of...
Provided by World Scientific Publishing
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White Papers
CTC: An End-to-End Flow Control Protocol for Multi-Core Systems-on-Chip
May 2009
The authors propose Connection Then Credits (CTC) as a new end-to-end flow control protocol to handle message-dependent deadlocks in Networks-on-Chip (NoC) for multi-core systems-on-chip. CTC is...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Distributed Flit-Buffer Flow Control for Networks-on-Chip
Oct 2008
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for Networks-on-Chip (NoC). Since they both rely on backpressure, the two techniques...
Provided by Association for Computing Machinery
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White Papers
A Methodology for Constraint-Driven Synthesis of On-Chip Communications
Mar 2009
The authors present a methodology and an optimization framework for the synthesis of on-chip communication through the assembly of components such as interfaces, routers, buses and links, from a...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
FPGA Real Time Acceleration for Discrete Wavelet Transform of the 5/3 Filter for JPEG2000 Standard
Mar 2012
In recent years video and image compression have became very required. The availability of powerful software design tools is a fundamental requirement to take advantage of the many advanced and...
Provided by Academy & Industry Research Collaboration Center
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White Papers
Design and Optimization of Full Comparator Based on Quantum-Dot Cellular Automata
Apr 2012
Quantum-dot Cellular Automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power...
Provided by ETRI Journal
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White Papers
CTC Turbo Decoding Architecture for LTE Systems Implemented on FPGA
Feb 2012
This paper describes a turbo decoder for Long Term Evolution (LTE) standard, release 8, using a Max Log MAP algorithm. The Forward Error Correction (FEC) block dimensions, as indicated in the...
Provided by IARIA
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White Papers
A Tool for Signal Probability Analysis of FPGA-Based Systems
Sep 2011
The authors describe a model of Field Programmable Gate Array based systems realised with the Stochastic Activity Networks formalism. The model can be used to debug the circuit design synthesised...
Provided by IARIA
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