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Mission Statement
TechRepublic's ITPapers is the Web's largest library of free technical IT white papers, webcasts, and case studies. Covering IT categories including Data Management, IT Management, Networking, Communications, Enterprise Applications, Storage, Security and much more, TechRepublic's White Paper Directory is the best source for technical white papers and IT information.
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White Papers
Multi-Threading Performance on Commodity Multi-Core Processors
Jun 2007
Multi-core processors based commodity servers recently become building blocks for high performance computing Linux clusters. The multi-core processors deliver better performance-to-cost ratios...
Provided by Jefferson Lab
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White Papers
WCET Analysis for Multi-Core Processors With Shared L2 Instruction Caches
Feb 2008
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able to accurately...
Provided by Southern Illinois University Carbondale
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White Papers
Composable Lightweight Processors
Sep 2007
Modern Chip MultiProcessors (CMPs) are designed to exploit both Instruction-Level Parallelism (ILP) within processors and Thread-Level Parallelism (TLP) within and across processors. However, the...
Provided by Intel
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White Papers
A Component-Based Visual Simulator for MIPS32 Processors
Aug 2008
Processor implementation and performance analysis are fundamental in computer architecture education. A processor can be described at different abstraction levels: a black box with inputs and...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Improving Offset Assignment for Embedded Processors
Jul 2007
Embedded systems consisting of the application program ROM, RAM, the embedded processor core, and any custom hardware on a single wafer are becoming increasingly common in application domains such...
Provided by Springer Science+Business Media
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White Papers
Simultaneous Multithreading: A Platform for Next-Generation Processors
Jan 2010
With the dizzying pace of semiconductor technology development, CPU designers are squeezing previously unimaginable amounts of hardware onto a single chip. Over the next 15 years the authors can...
Provided by University of Washington
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White Papers
Measuring Power and Temperature From Real Processors
Feb 2008
The modeling of power and thermal behavior of modern processors requires challenging validation approaches, which may be complex and in some cases unreliable. In order to address some of the...
Provided by University of California, Santa Cruz
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White Papers
Parallel Evidence Propagation on Multicore Processors
May 2009
In this paper designs and implements an efficient technique for parallel evidence propagation on state-of-the-art multicore processor systems. Evidence propagation is a major step in exact...
Provided by Tsinghua University
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White Papers
The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling
Jun 2008
Although most current multicore processors are homogeneous, microarchitects are now proposing heterogeneous core implementations, including systems in which heterogeneity is introduced at runtime....
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Built-In Self-Test of Digital Signal Processors in Virtex-4 FPGAs
Mar 2009
This paper present a Built-In Self-Test (BIST) approach for testing and diagnosing the embedded Digital Signal Processors (DSPs) in Xilinx Virtex-4 series Field Programmable Gate Arrays (FPGAs)....
Provided by Auburn University
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White Papers
An Adaptive Resource Partitioning Algorithm in SMT Processors
Mar 2008
Simultaneous MultiThreading (SMT) increases processor throughput by allowing the parallel execution of several threads. However, fully sharing processor re-sources may cause resource...
Provided by University of Massachusetts
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White Papers
Specialty Processors
Jan 2008
Marketplace pressures have increased demand for high quality computer graphics. Scientists use images to interpret lab data more effectively, and multimedia demands for computers are always...
Provided by Oregon State University
-
White Papers
Multi Processors, Their Memory Organizations and Implementations by Intel & AMD
Nov 2008
Multi-core processors represent a major evolution in computing technology and are becoming very popular today. Multi-core processors will eventually become the pervasive computing model because...
Provided by Electronic Visualization Laboratory
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White Papers
Miss Reduction in Embedded Processors Through Dynamic, Power-Friendly Cache Design
Jun 2008
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result, traditional...
Provided by Association for Computing Machinery
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White Papers
Modeling Multigrain Parallelism on Heterogeneous Multi-Core Processors: A Case Study of the Cell BE
Nov 2007
Heterogeneous multi-core processors invest the most significant portion of their transistor budget in customized "Accelerator" cores, while using a small number of conventional low-end cores for...
Provided by Virginia Polytechnic Institute and State University
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White Papers
StimulusCache: Boosting Performance of Chip Multiprocessors With Excess Cache
Jan 2010
Technology advances continuously shrink on-chip devices. Consequently, the number of cores in a single Chip Multiprocessor (CMP) is expected to grow in coming years. Unfortunately, with smaller...
Provided by University of Pittsburgh
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White Papers
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
Nov 2008
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient shared cache...
Provided by Springer Science+Business Media
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White Papers
Fully Accessible Touch Screens for the Blind and Visually Impaired
May 2009
Recent advances in touch screen technology have increased the usability of touch screens for sighted users and prompted a wave of new touch screen-based devices. However, touch screens are still...
Provided by University of Washington
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White Papers
Low-Power Branch Target Buffer for Application-Specific Embedded Processors
Jan 2011
In this paper the authors present a methodology for a low-power branch identification mechanism, which enables the design of extremely power efficient branch predictors for embedded processors....
Provided by University of California, San Diego
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White Papers
Adapting to Intermittent Faults in Future Multicore Systems
Jul 2007
As technology continues to scale, future multicore processors become more susceptible to a variety of hardware failures. In particular, intermittent faults are expected to become especially...
Provided by University of Wisconsin
-
White Papers
Tamper Evident Microprocessors
Apr 2010
Most security mechanisms proposed to date unquestioningly place trust in microprocessor hardware. This trust, however, is misplaced and dangerous because microprocessors are vulnerable to insider...
Provided by Columbia University
-
White Papers
Motherboards Deliver Long-Life Availability
May 2009
How does one define obsolete in the ever-changing embedded-computing-technology industry? If an engineer is using a standard off-the-shelf motherboard in an embedded application, the product is in...
Provided by Extension Media
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White Papers
Slide Rule: Making Mobile Touch Screens Accessible to Blind People Using Multi-Touch Interaction Techniques
Oct 2008
Recent advances in touch screen technology have increased the prevalence of touch screens and have prompted a wave of new touch screen-based devices. However, touch screens are still largely...
Provided by Association for Computing Machinery
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White Papers
Isolation in Commodity Multicore Processors
Jun 2007
Technology scaling and power trends have led to the widespread emergence of Chip Multiprocessors (CMPs) as the predominant hardware paradigm. 1 Multiple cores are being integrated on a single chip...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Modeling and Simulation of Legacy Embedded Systems
Apr 2010
This paper describes a modeling formalism that specifically addresses description and performance analysis of simulators for legacy real-time embedded systems. The proposed framework includes the...
Provided by University of California, Berkeley
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White Papers
Simulation and Implementation of the PTIDES Programming Model
Oct 2008
The authors have previously proposed PTIDES (Programming Temporally Integrated Distributed Embedded Systems), a discrete event framework that binds realtime with model time at sensors, actuators,...
Provided by University of California, Berkeley
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White Papers
Optimizing a Multi-Core Processor for Message-Passing Workloads
Apr 2009
Future large-scale multi-cores will likely be best suited for use within High-Performance Computing (HPC) domains. A large fraction of HPC workloads employ the Message Passing Interface (MPI), yet...
Provided by University of Utah
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White Papers
Execution Strategies for PTIDES, a Programming Model for Distributed Embedded Systems
Apr 2009
This paper defines a family of execution policies for a programming model called PTIDES (Programming Temporally Integrated Distributed Embedded Systems). A PTIDES application (Factory automation,...
Provided by University of California, Berkeley
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White Papers
Application of Combined Discrete-Event Simulation and Optimization Models in Semiconductor Enterprise Manufacturing Systems
Jul 2007
It is a common practice to use simulation for validating different types of control and planning algorithms. However, the science of how to rigorously integrate simulation and decision models is...
Provided by Arizona State University
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White Papers
EXACT: Explicit Dynamic-Branch Prediction With Active Updates
May 2010
Branches that depend directly or indirectly on load instructions are a leading cause of mispredictions by state-of-the-art branch predictors. For a branch of this type, there is a unique dynamic...
Provided by Association for Computing Machinery
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White Papers
A 65 nm 2-Billion Transistor Quad-Core Itanium Processor
Jan 2009
This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
An Experimental Laboratory Environment for Teaching Embedded Hardware Systems
Jun 2007
This paper presents the prototype for an experimental embedded systems laboratory and the design for an introductory hardware systems course based on that laboratory. The degree to which...
Provided by Association for Computing Machinery
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White Papers
Open and Easy Microprocessor Designs Using the LatticeMico32
Feb 2008
Three important benefits of the embedded microprocessor approach are driving this trend. The first is that a soft processor provides the preferred way to implement control-plane functionality in...
Provided by Lattice Semiconductor
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White Papers
OCP-IP Network-on-Chip Benchmarking Workgroup
Dec 2010
This article presents a summary of the work and infrastructure developed by the OCP-IP Network-on-Chip benchmarking workgroup. Network-on-chip (NoC) is an emerging paradigm for interconnecting...
Provided by Tampere University of Technology
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White Papers
Characterization of Embedded Applications for Decoupled Processor Architecture
Jan 2011
Needs for performance on embedded applications will lead to the use of dynamic execution on embedded processors in the next few years. However, complete out-of-order superscalar cores are still...
Provided by IRISA
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White Papers
Framework for Improving Parallelism by Write-Update Coherence Protocol in Distributed Shared Memory System
May 2008
For increasing parallelism in DSM System, the replication of data is to be done. The replication of data increases parallelism by allowing reads of the same data to be executed in parallel....
Provided by Academy Publisher
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White Papers
Reliability and Fault Tolerance of Ultra Low Voltage High Speed Differential CMOS
Mar 2009
The reliability and fault tolerance of the differential ultra low voltage gate is elaborated in this paper. The gates optimal yield and defect tolerance compared to ULV gate and standard CMOS is...
Provided by University of Oslo
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White Papers
Design of a Numerical Adaptive Relay Based on Memory Mapped Techniques
Mar 2009
This work describes the design of a DSP (Digital Signal Processor) based Adaptive Numerical Mho relay, to be used for distance protection schemes of long distance transmission lines. The relay...
Provided by International Association of Engineers
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White Papers
CNC System of MKS1632 External Cylindrical Grinding Machines Based on Embedded
Apr 2010
The traditional CNC system based on the IPC is complex structure, high cost, hardware redundancy and can not be cut, high power consumption and low reliability, this paper proposed and designed a...
Provided by Academy Publisher
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White Papers
Enhanced Energy-Aware Feedback Scheduling of Embedded Control Systems
Feb 2009
Dynamic Voltage Scaling (DVS) is one of the most effective techniques for reducing energy consumption in embedded and real-time systems. However, traditional DVS algorithms have inherent...
Provided by Academy Publisher
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Whitepapers
One Stone Two Birds: Synchronization Relaxation and Redundancy Removal in GPU-CPU Translation
Jun 2012
As an approach to promoting whole-system synergy on a heterogeneous computing system, compilation of fine-grained SPMD-threaded code (e.g., GPU CUDA code) for multicore CPU has drawn some recent...
Provided by Association for Computing Machinery
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Whitepapers
Enhancing Data Locality for Dynamic Simulations Through Asynchronous Data Transformations and Adaptive Control
Aug 2011
Many dynamic simulation programs contain complex, irregular memory reference patterns, and require runtime optimizations to enhance data locality. Current approaches periodically stop the...
Provided by College of William and Mary
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Whitepapers
Correctly Treating Synchronizations in Compiling Fine-Grained SPMD-Threaded Programs for CPU
Aug 2011
Automatic compilation for multiple types of devices is important, especially given the current trends towards heterogeneous computing. This paper concentrates on some issues in compiling...
Provided by College of William and Mary
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Whitepapers
SysGen Architecture for Visual Information Hiding Framework
Mar 2012
The development time and cost for DSP solution have been improved significantly due to proliferation of rapid prototyping tools such as MATLAB-Simulink and Xilinx System Generator (SysGen). The...
Provided by International Journal of Emerging Technology and Advanced Engineering (IJETAE)
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Whitepapers
Brute Force Methodology of Hardware/Software Co-Design
Jun 2012
Design of embedded systems is becoming increasingly difficult due to the tight constraints on area usage, size, power consumption and performance. In addition to these one more constraint faced in...
Provided by International Journal of Computer Technology and Electronics Engineering
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Whitepapers
A New Process Model for Embedded Systems Control for Telecom Industry
Sep 2012
This paper deals with important issue for the embedded system in telecom industry. The rapid increase of a software and software based functionality brings various challenges for the telecom...
Provided by Engg Journals Publications
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Whitepapers
Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs
Feb 2012
Many True Random Numbers Generators (TRNG) use jittery clocks generated in ring oscillators as a source of entropy. This is especially the case in Field Programmable Gate Arrays (FPGA), where...
Provided by INRIA
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Whitepapers
Architectural Review: Evolution of Embedded Digital Signal Processors
Apr 2012
Digital Signal Processing is one of the most powerful technologies that will shape science and engineering in the twenty-first century. Revolutionary changes have already been made in a broad...
Provided by International Journal of Emerging Technology and Advanced Engineering (IJETAE)
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Whitepapers
Design and Implementation of 5 Stages Pipelined Architecture in 32 Bit RISC Processor
Apr 2012
The proposed paper is the design of a 32 bit RISC (Reduced Instruction Set Computer) processor. The design will help to improve the speed of processor, and to give the higher performance of the...
Provided by International Journal of Emerging Technology and Advanced Engineering (IJETAE)
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Whitepapers
Explore the Performance of the ARM Processor Using Protocol Trainer
Apr 2012
Recently, the evolution of embedded systems has shown a strong trend towards application specific, single chip solutions. The ARM processor core is a leading RISC processor architecture in the...
Provided by International Journal of Computer Technology and Electronics Engineering
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Whitepapers
A Practical Dynamic Frequency Scaling Scheduling Algorithm for General Purpose Embedded Operating System
Jan 2009
Dynamic frequency scaling (DFS) techniques for real-time embedded systems have been widely studied. However, most of the scheduling algorithms so far concern only special purpose real-time...
Provided by Science and Development Network (SciDev.Net)
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Whitepapers
Design and Implementation of Viterbi Encoder and Decoder Using FPGA
Jun 2012
In this paper, the authors present an implementation of the Viterbi algorithm using the Hardware Description Language and Implemented on FPGA. They begin with a description of the algorithm....
Provided by International Journal of Engineering and Advanced Technology (IJEAT)
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Whitepapers
FPGA Based an Advanced Lut Methodology for Design of a Digital Filter
Feb 2012
The present manuscript proposes an advanced methodology based on which the LUT is modeled through which an FIR filter is designed for efficient area utilization. As it is a known fact that most of...
Provided by INTERNATIONAL JOURNAL OF ENGINEERING SCIENCE & ADVANCED TECHNOLOGY
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Whitepapers
A Case Study on Design and Evaluation of Modified Adaptive Fuzzy Pid Controller
Dec 2011
Most of process control systems are based on PID controllers, because of their remarkable effectiveness, simplicity and robustness, As PID controller design theory and practical procedures are...
Provided by Journal of Global Research in Computer Science (JGRCS)
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Whitepapers
Implementation of AHB Bus Tracer With Dynamic Multiresolution for Lossless Real Time Compression
Jun 2012
In the System-on-Chip (SoC) debugging and performance analysis/optimization, monitoring the on-chip bus signals are necessary. But, such signals are difficult to observe since they are deeply...
Provided by INTERNATIONAL JOURNAL OF ENGINEERING SCIENCE & ADVANCED TECHNOLOGY
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Whitepapers
A Novel Technique for Real-Time Internet Radio Recorder on Non-DSP Embedded System
Jul 2008
The capability of providing real-time multimedia player over the Internet is an important future application for embedded system. However, the main challenge of such an application is the...
Provided by Science and Development Network (SciDev.Net)
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Whitepapers
On the Association of Power-Flow With Circuit Terminals
Oct 2011
In classical circuit theory, the question of how much power flows into a circuit through a set of terminals only makes sense if these terminals form a port, i.e., if the sum of the terminal...
Provided by Institute of Electrical & Electronic Engineers
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Whitepapers
Effect of Electrostatic Discharge on Digital and Analog Circuits
Aug 2012
A comparative study of the effects of ElectroStatic Discharge (ESD) on digital and analog circuits is carried out. Direct and Indirect discharge is performed on the circuit having both analog and...
Provided by IOSR Journal of Engineering
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Whitepapers
Design of High Speed Reconfigurable Coprocessor for Multiplier/Adder and Subtractions Operations
Oct 2012
As the quantity of data transmission and reception increases, there is a gradual increase in bandwidth on demand and quality of service. This further increases data traffic which leads to loss of...
Provided by IOSR Journal of Engineering
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Whitepapers
System Development Process Based on Embedded Linux and Sensor Node
Apr 2012
Embedded systems are suitable for application system with strict requirements on the functionality, reliability, cost, size and power consumption Also embedded Linux has been widely used to its...
Provided by Science and Development Network (SciDev.Net)
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Whitepapers
eEmbedding Activity Theory Into CommonKADS as Knowledge Elicitation Technique
Jun 2012
Eliciting knowledge is the key to build large and powerful Knowledge-Based Systems (KBSs) that are capable of solving problems or giving advice. In this view, knowledge elicitation is the work a...
Provided by International Journal of Information Technology & Computer Science ( IJITCS )
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Whitepapers
Opportunistic Scheduler Evaluation Using Discriminatory Processor Sharing Model
Apr 2008
This paper studies the flow-level performance of a special family of weight-based opportunistic scheduler using Discriminatory Processor Sharing (DPS) model. It is known that this family of...
Provided by Institute of Electrical & Electronic Engineers
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Whitepapers
The Performance Analysis of Fast DCT Algorithms on Parallel Cluster Architecture
May 2012
Clustered processor, having 16 clusters with 4 PE's in each cluster and each PE having two ALU, which can perform simultaneously, is taken. The PE's operate in a SIMD manner. The cluster and PE...
Provided by International Journal of Information and Electronics Engineering
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Whitepapers
Data Transmission at 12kb/s Over 32kb/s ADPCM
May 2012
This paper presents new modified QAM modem that operates at data rate of 12kb/s to be transmitted over 32kb/s Adaptive Differential Pulse Code Modulation (ADPCM). The purpose of this modified QAM...
Provided by International Journal of Information and Electronics Engineering
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Whitepapers
Performance Assessment of Some CPU Scheduling Algorithms
Aug 2009
The problem of scheduling which computer process run at what time on the Central Processing Unit (CPU) or the processor is explored. Three basic CPU scheduling algorithms (namely first come first...
Provided by Maxwell Science Publication
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Whitepapers
A Comparative Study of the MPI Communication Primitives on a Cluster
Oct 2008
MPI (Message Passing Interface) has become the de facto standard for implementing parallel programs on distributed systems. In MPI, the two basic communication primitives are point-to-point...
Provided by National Institute of Technology, Durgapur
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Whitepapers
MPSoC Bus Architecture Optimization Under Performance Constraints for Multiple Applications
Sep 2009
Optimization of interconnects among processors and memories becomes important as multiple processors and memories can be integrated on a Multi-Processor System-on-Chip (MPSoC). Since the optimal...
Provided by Institute of Electrical & Electronic Engineers
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Whitepapers
Cipher and Media Possibility of a Ubiquitous Processor
Sep 2009
Power conscious strong security and multimedia reality are demanded for the construction of emerging ubiquitous environment. Since multimedia computing requires high performance, high precision,...
Provided by Institute of Electrical & Electronic Engineers
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Whitepapers
A Novel, Low-Power Array Multiplier Architecture
Sep 2009
Low power parallel array multiplier is proposed for both unsigned and two's complement signed multiplication. Modified Baugh-Wooley multiplier is further modified and if input numbers are not in...
Provided by Institute of Electrical & Electronic Engineers
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Whitepapers
Performance of Ethernet Protocol Conversion on an Arm-7 Embedded Processor
Apr 2012
This paper designed a research on real web access functionality is embedded in a device to enable low cost widely accessible and enhanced user interface functions for the device. A web server in...
Provided by International Journal of Engineering Trends and Technology
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Whitepapers
FPGA Based Area and Throughput Implementation of JH and BLAKE Hash Function
Apr 2012
Implementation of area and throughput of the main building block (compression function) for two SHA-3 candidates BLAKE and JH hash function. The National Institute of Standards and Technology...
Provided by IJCTT-International Journal of Computer Trends and Technology
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Whitepapers
Implementation of SOBEL Edge Detection on FPGA
Jun 2012
The image processing algorithms has been limited to software implementation which is slower due to the limited processor speed. So, a dedicated processor for edge detection is required which was...
Provided by IJCTT-International Journal of Computer Trends and Technology
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Whitepapers
A New Reduced Clock Power Flip-Flop for Future SOC Applications
Aug 2012
In this paper a novel technique is proposed based on the comparison between Conventional Conditional Data Mapping Flip-flop and Clock Pair Shared D Flip Flop (CPSFF) here the authors are checking...
Provided by IJCTT-International Journal of Computer Trends and Technology
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Whitepapers
Implementation of GALS Chip Multiprocessor With Flexibly Configurable Low Latency Interconnect
Oct 2011
Chip Multiprocessors with flexible configuration capability and with reduced latency is implemented in FPGA with reduced area utilization. Globally Asynchronous Locally Synchronous (GALS) design...
Provided by International forum of researchers Students and Academician
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Whitepapers
FPGA and ASIC Implementation of Vedic Multiplier
Jul 2012
The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip....
Provided by International forum of researchers Students and Academician
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Whitepapers
Resource Sharing Control in Simultaneous MultiThreading Microarchitectures
Mar 2008
Simultaneous MultiThreading (SMT) achieves improved system resource utilization and accordingly higher instruction throughput because it exploits Thread-Level Parallelism (TLP) in addition to...
Provided by University of California
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Whitepapers
PCOUNT: A Power Aware Fetch Policy in Simultaneous Multithreading Processors
Jun 2011
The Simultaneous Multi-Threading (SMT) architecture improves the resource efficiency via scheduling and executing concurrent threads in the same core. Moreover, fetch policies are proposed to...
Provided by Florida International University
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Whitepapers
Stochastic Computing: Embracing Errors in Architecture and Design of Processors and Applications
Oct 2011
As device sizes shrink, device-level manufacturing challenges have led to increased variability in physical circuit characteristics. Exponentially increasing circuit density has not only brought...
Provided by Association for Computing Machinery
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Whitepapers
On Software Design for Stochastic Processors
Jun 2012
Much recent research suggests significant power and energy benefits of relaxing correctness constraints in future processors. Such processors with relaxed constraints have often been referred to...
Provided by Association for Computing Machinery
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Whitepapers
A Multi Variable Optimization Approach for the Design of Integrated Dependable Real-Time Embedded Systems
Oct 2007
Embedded systems increasingly encompass both dependability and responsiveness requirements. While sophisticated techniques exist, on a discrete basis, for both dependability/Fault-Tolerance (FT)...
Provided by International Federation for Information Processing
-
White Papers
Composable Lightweight Processors
Sep 2007
Modern Chip MultiProcessors (CMPs) are designed to exploit both Instruction-Level Parallelism (ILP) within processors and Thread-Level Parallelism (TLP) within and across processors. However, the...
Provided by Intel
-
White Papers
A Component-Based Visual Simulator for MIPS32 Processors
Aug 2008
Processor implementation and performance analysis are fundamental in computer architecture education. A processor can be described at different abstraction levels: a black box with inputs and...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Improving Offset Assignment for Embedded Processors
Jul 2007
Embedded systems consisting of the application program ROM, RAM, the embedded processor core, and any custom hardware on a single wafer are becoming increasingly common in application domains such...
Provided by Springer Science+Business Media
-
White Papers
Simultaneous Multithreading: A Platform for Next-Generation Processors
Jan 2010
With the dizzying pace of semiconductor technology development, CPU designers are squeezing previously unimaginable amounts of hardware onto a single chip. Over the next 15 years the authors can...
Provided by University of Washington
-
White Papers
Measuring Power and Temperature From Real Processors
Feb 2008
The modeling of power and thermal behavior of modern processors requires challenging validation approaches, which may be complex and in some cases unreliable. In order to address some of the...
Provided by University of California, Santa Cruz
-
White Papers
Parallel Evidence Propagation on Multicore Processors
May 2009
In this paper designs and implements an efficient technique for parallel evidence propagation on state-of-the-art multicore processor systems. Evidence propagation is a major step in exact...
Provided by Tsinghua University
-
White Papers
The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling
Jun 2008
Although most current multicore processors are homogeneous, microarchitects are now proposing heterogeneous core implementations, including systems in which heterogeneity is introduced at runtime....
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Built-In Self-Test of Digital Signal Processors in Virtex-4 FPGAs
Mar 2009
This paper present a Built-In Self-Test (BIST) approach for testing and diagnosing the embedded Digital Signal Processors (DSPs) in Xilinx Virtex-4 series Field Programmable Gate Arrays (FPGAs)....
Provided by Auburn University
-
White Papers
An Adaptive Resource Partitioning Algorithm in SMT Processors
Mar 2008
Simultaneous MultiThreading (SMT) increases processor throughput by allowing the parallel execution of several threads. However, fully sharing processor re-sources may cause resource...
Provided by University of Massachusetts
-
White Papers
Specialty Processors
Jan 2008
Marketplace pressures have increased demand for high quality computer graphics. Scientists use images to interpret lab data more effectively, and multimedia demands for computers are always...
Provided by Oregon State University
-
White Papers
Multi Processors, Their Memory Organizations and Implementations by Intel & AMD
Nov 2008
Multi-core processors represent a major evolution in computing technology and are becoming very popular today. Multi-core processors will eventually become the pervasive computing model because...
Provided by Electronic Visualization Laboratory
-
White Papers
Miss Reduction in Embedded Processors Through Dynamic, Power-Friendly Cache Design
Jun 2008
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result, traditional...
Provided by Association for Computing Machinery
-
White Papers
Modeling Multigrain Parallelism on Heterogeneous Multi-Core Processors: A Case Study of the Cell BE
Nov 2007
Heterogeneous multi-core processors invest the most significant portion of their transistor budget in customized "Accelerator" cores, while using a small number of conventional low-end cores for...
Provided by Virginia Polytechnic Institute and State University
-
White Papers
StimulusCache: Boosting Performance of Chip Multiprocessors With Excess Cache
Jan 2010
Technology advances continuously shrink on-chip devices. Consequently, the number of cores in a single Chip Multiprocessor (CMP) is expected to grow in coming years. Unfortunately, with smaller...
Provided by University of Pittsburgh
-
White Papers
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
Nov 2008
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient shared cache...
Provided by Springer Science+Business Media
-
White Papers
Fully Accessible Touch Screens for the Blind and Visually Impaired
May 2009
Recent advances in touch screen technology have increased the usability of touch screens for sighted users and prompted a wave of new touch screen-based devices. However, touch screens are still...
Provided by University of Washington
-
White Papers
Low-Power Branch Target Buffer for Application-Specific Embedded Processors
Jan 2011
In this paper the authors present a methodology for a low-power branch identification mechanism, which enables the design of extremely power efficient branch predictors for embedded processors....
Provided by University of California, San Diego
-
White Papers
Adapting to Intermittent Faults in Future Multicore Systems
Jul 2007
As technology continues to scale, future multicore processors become more susceptible to a variety of hardware failures. In particular, intermittent faults are expected to become especially...
Provided by University of Wisconsin
-
White Papers
Tamper Evident Microprocessors
Apr 2010
Most security mechanisms proposed to date unquestioningly place trust in microprocessor hardware. This trust, however, is misplaced and dangerous because microprocessors are vulnerable to insider...
Provided by Columbia University
-
White Papers
Motherboards Deliver Long-Life Availability
May 2009
How does one define obsolete in the ever-changing embedded-computing-technology industry? If an engineer is using a standard off-the-shelf motherboard in an embedded application, the product is in...
Provided by Extension Media
-
White Papers
Slide Rule: Making Mobile Touch Screens Accessible to Blind People Using Multi-Touch Interaction Techniques
Oct 2008
Recent advances in touch screen technology have increased the prevalence of touch screens and have prompted a wave of new touch screen-based devices. However, touch screens are still largely...
Provided by Association for Computing Machinery
-
White Papers
Isolation in Commodity Multicore Processors
Jun 2007
Technology scaling and power trends have led to the widespread emergence of Chip Multiprocessors (CMPs) as the predominant hardware paradigm. 1 Multiple cores are being integrated on a single chip...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Modeling and Simulation of Legacy Embedded Systems
Apr 2010
This paper describes a modeling formalism that specifically addresses description and performance analysis of simulators for legacy real-time embedded systems. The proposed framework includes the...
Provided by University of California, Berkeley
-
White Papers
Simulation and Implementation of the PTIDES Programming Model
Oct 2008
The authors have previously proposed PTIDES (Programming Temporally Integrated Distributed Embedded Systems), a discrete event framework that binds realtime with model time at sensors, actuators,...
Provided by University of California, Berkeley
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White Papers
Optimizing a Multi-Core Processor for Message-Passing Workloads
Apr 2009
Future large-scale multi-cores will likely be best suited for use within High-Performance Computing (HPC) domains. A large fraction of HPC workloads employ the Message Passing Interface (MPI), yet...
Provided by University of Utah
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White Papers
Execution Strategies for PTIDES, a Programming Model for Distributed Embedded Systems
Apr 2009
This paper defines a family of execution policies for a programming model called PTIDES (Programming Temporally Integrated Distributed Embedded Systems). A PTIDES application (Factory automation,...
Provided by University of California, Berkeley
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White Papers
Application of Combined Discrete-Event Simulation and Optimization Models in Semiconductor Enterprise Manufacturing Systems
Jul 2007
It is a common practice to use simulation for validating different types of control and planning algorithms. However, the science of how to rigorously integrate simulation and decision models is...
Provided by Arizona State University
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White Papers
EXACT: Explicit Dynamic-Branch Prediction With Active Updates
May 2010
Branches that depend directly or indirectly on load instructions are a leading cause of mispredictions by state-of-the-art branch predictors. For a branch of this type, there is a unique dynamic...
Provided by Association for Computing Machinery
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White Papers
A 65 nm 2-Billion Transistor Quad-Core Itanium Processor
Jan 2009
This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
An Experimental Laboratory Environment for Teaching Embedded Hardware Systems
Jun 2007
This paper presents the prototype for an experimental embedded systems laboratory and the design for an introductory hardware systems course based on that laboratory. The degree to which...
Provided by Association for Computing Machinery
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White Papers
Open and Easy Microprocessor Designs Using the LatticeMico32
Feb 2008
Three important benefits of the embedded microprocessor approach are driving this trend. The first is that a soft processor provides the preferred way to implement control-plane functionality in...
Provided by Lattice Semiconductor
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White Papers
OCP-IP Network-on-Chip Benchmarking Workgroup
Dec 2010
This article presents a summary of the work and infrastructure developed by the OCP-IP Network-on-Chip benchmarking workgroup. Network-on-chip (NoC) is an emerging paradigm for interconnecting...
Provided by Tampere University of Technology
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White Papers
Characterization of Embedded Applications for Decoupled Processor Architecture
Jan 2011
Needs for performance on embedded applications will lead to the use of dynamic execution on embedded processors in the next few years. However, complete out-of-order superscalar cores are still...
Provided by IRISA
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White Papers
Framework for Improving Parallelism by Write-Update Coherence Protocol in Distributed Shared Memory System
May 2008
For increasing parallelism in DSM System, the replication of data is to be done. The replication of data increases parallelism by allowing reads of the same data to be executed in parallel....
Provided by Academy Publisher
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White Papers
Reliability and Fault Tolerance of Ultra Low Voltage High Speed Differential CMOS
Mar 2009
The reliability and fault tolerance of the differential ultra low voltage gate is elaborated in this paper. The gates optimal yield and defect tolerance compared to ULV gate and standard CMOS is...
Provided by University of Oslo
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White Papers
Design of a Numerical Adaptive Relay Based on Memory Mapped Techniques
Mar 2009
This work describes the design of a DSP (Digital Signal Processor) based Adaptive Numerical Mho relay, to be used for distance protection schemes of long distance transmission lines. The relay...
Provided by International Association of Engineers
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White Papers
CNC System of MKS1632 External Cylindrical Grinding Machines Based on Embedded
Apr 2010
The traditional CNC system based on the IPC is complex structure, high cost, hardware redundancy and can not be cut, high power consumption and low reliability, this paper proposed and designed a...
Provided by Academy Publisher
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White Papers
Enhanced Energy-Aware Feedback Scheduling of Embedded Control Systems
Feb 2009
Dynamic Voltage Scaling (DVS) is one of the most effective techniques for reducing energy consumption in embedded and real-time systems. However, traditional DVS algorithms have inherent...
Provided by Academy Publisher
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White Papers
A Compact Architecture for Montgomery Elliptic Curve Scalar Multiplication Processor
Sep 2007
This paper proposes a compact architecture of a Montgomery elliptic curve scalar multiplier in a projective coordinate system over GF (2m). To minimize the gate area of the architecture, the...
Provided by Katholieke Universiteit Leuven
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White Papers
Cross Layer Design to Multi-Thread a Data-Pipelining Application on a Multi-Processor on Chip
Jan 2011
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor platform spans...
Provided by Boston University
