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Mission Statement
TechRepublic's ITPapers is the Web's largest library of free technical IT white papers, webcasts, and case studies. Covering IT categories including Data Management, IT Management, Networking, Communications, Enterprise Applications, Storage, Security and much more, TechRepublic's White Paper Directory is the best source for technical white papers and IT information.
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White Papers
INVISIFENCE: Performance-Transparent Memory Ordering in Conventional Multiprocessors
Jun 2009
A multiprocessor's memory consistency model imposes ordering constraints among loads, stores, atomic operations, and memory fences. Even for consistency models that relax ordering among loads and...
Provided by Association for Computing Machinery
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White Papers
Towards Controllable Distributed Real-Time Systems With Feasible Utilization Control
Aug 2009
Feedback control techniques have recently been applied to a variety of real-time systems. However, a fundamental issue that was left out is guaranteeing system controllability and the feasibility...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
To GPU Synchronize or Not GPU Synchronize?
Mar 2010
The Graphics Processing Unit (GPU) has evolved from being a fixed-function processor with programmable stages into a programmable processor with many fixed-function components that deliver massive...
Provided by Virginia Tech
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White Papers
Inter-Block GPU Communication Via Fast Barrier Synchronization
Mar 2010
While GPGPU stands for General-Purpose computation on Graphics Processing Units, the lack of explicit support for inter-block communication on the GPU arguably hampers its broader adoption as a...
Provided by Virginia Tech
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White Papers
On the Robust Mapping of Dynamic Programming Onto a Graphics Processing Unit
Dec 2009
Graphics Processing Units (GPUs) have been widely used to accelerate algorithms that exhibit massive data parallelism or task parallelism. When such parallelism is not inherent in an algorithm,...
Provided by Virginia Tech
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White Papers
Virtual Hierarchies
Feb 2008
Memory system hierarchies are fundamental to computing systems. They have long improved performance because most programs temporally concentrate accesses to code and data. However, emerging...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Forward flow: A Scalable Core for Power-Constrained CMPs
Apr 2010
Chip MultiProcessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased core per-socket count will...
Provided by Association for Computing Machinery
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White Papers
Calvin: Deterministic or Not? Free Will to Choose
Dec 2010
Most shared memory systems maximize performance by unpredictably resolving memory races. Unpredictable memory races can lead to non-determinism in parallel programs, which can suffer from...
Provided by University of Wisconsin-Madison
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White Papers
Two Hardware-Based Approaches for Deterministic Multiprocessor Replay
Jun 2009
Many shared-memory multithreaded executions behave non-deterministically when run on multiprocessor hardware such as emerging multicore systems. Recording nondeterministic events in such...
Provided by Association for Computing Machinery
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White Papers
Active Storage Revisited: The Case for Power and Performance Benefits for Unstructured Data Processing Applications
May 2008
The proliferation of digital data has resulted in a mushrooming of data-intensive applications, especially in the area of unstructured data processing. Given the growing popularity of unstructured...
Provided by Association for Computing Machinery
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White Papers
Compiler and Runtime Support for Enabling Generalized Reduction Computations on Heterogeneous Parallel Configurations
Jun 2010
A trend that has materialized, and has given rise to much attention, is of the increasingly heterogeneous computing platforms. Presently, it has become very common for a desktop or a notebook...
Provided by Association for Computing Machinery
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White Papers
Balancing Soft Error Coverage With Lifetime Reliability in Redundantly Multithreaded Processors
Jun 2009
Silicon reliability is a key challenge facing the micro-processor industry. Processors need to be designed such that they are resilient against both soft errors and lifetime reliability phenomena....
Provided by University of Virginia
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White Papers
PEEP: Exploiting Predictability of Memory Dependences in SMT Processors
Jan 2008
Simultaneous MultiThreading (SMT) attempts to keep a dynamically scheduled processor's resources busy with work from multiple independent threads. Threads with long-latency stalls, however, can...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
An Evaluation of Hash Functions on a Power Analysis Resistant Processor Architecture
Dec 2010
Cryptographic hash functions are omnipresent components in security-critical software and devices; they support, for example, digital signature and data authenticity schemes, mechanisms for key...
Provided by University of Bristol
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White Papers
Epoch Parallelism: One Execution Is Not Enough
Sep 2010
The conventional approach for using multiprocessors requires programmers to write correct, scalable parallel programs. Unfortunately, writing such programs remains a daunting task, despite decades...
Provided by University of Michigan
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White Papers
Runahead Threads to Improve SMT Performance
Apr 2008
In this paper, the authors propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded (SMT)...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect
Apr 2008
In this paper, the authors explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core Network-on-Chip...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Automated Microprocessor Stressmark Generation
Apr 2008
Estimating the maximum power and thermal characteristics of a processor is essential for designing its power delivery system, packaging, cooling, and power/thermal management schemes. Typical...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs
Apr 2008
The interconnect mechanisms (shared bus or crossbar) used in current Chip-Multi Processors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling to a larger...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Gaining Insights Into Multicore Cache Partitioning: Bridging the Gap Between Simulation and Real Systems
Apr 2008
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often has several...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
DeCoR: A Delayed Commit and Rollback Mechanism for Handling Inductive Noise in Processors
Apr 2008
Increases in peak current draw and reductions in the operating voltage of processors stress the importance of dealing with voltage fluctuations in processors. Noise-margin violations lead to...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Speculative Instruction Validation for Performance-Reliability Trade-Off
Apr 2008
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant Multi-Threading (RMT)...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Design and Implementation of the Blue Gene/P Snoop Filter
Jan 2008
As multi-core processors evolve, coherence traffic between cores is becoming problematic, both in terms of performance and power. The negative effects of coherence (snoop) traffic can be...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A Digital Rights Enabled Graphics Processing System
Jan 2011
With the emergence of 3D graphics/arts assets commerce on the Internet, to protect their intellectual property and to restrict their usage have become a new design challenge. This paper presents a...
Provided by EUROGRAPHICS Association
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White Papers
Dynamic Iterations for the Solution of Ordinary Differential Equations on Multicore Processors
Feb 2009
In the past few years, there has been a trend of providing increased computing power through greater number of cores on a chip, rather than through higher clock speeds. In order to exploit the...
Provided by Florida State University
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White Papers
Optimizing Assignment of Threads to SPEs on the Cell BE Processor
Feb 2009
The Cell is a heterogeneous multicore processor that has attracted much attention in the HPC community. The bulk of the computational workload on the Cell processor is carried by eight...
Provided by Florida State University
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White Papers
Distributed Estimation and Coding: A Sequential Framework Based on a Side-Informed Decomposition
Feb 2011
The authors propose a sequential framework for the distributed multiple-sensor estimation and coding problem that decomposes the problem into a series of side-informed source coding problems and...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
CellSort: High Performance Sorting on the Cell Processor
Sep 2007
In this paper the authors describe the design and implementation of CellSort a high performance distributed sort algorithm for the Cell processor. They design CellSort as a distributed bitonic...
Provided by Association for Computing Machinery
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White Papers
Adaptive Aggregation on Chip Multiprocessors
Sep 2007
The recent introduction of commodity chip multiprocessors requires that the design of core database operations be care-fully examined to take full advantage of on-chip parallelism. In this paper...
Provided by Association for Computing Machinery
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White Papers
GPU Computing
Oct 2009
The Graphics Processing Unit (GPU) has become an integral part of today's mainstream computing systems. Over the past six years, there has been a marked increase in the performance and...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Area-Efficiency in CMP Core Design: Co-Optimization of Microarchitecture and Physical Design
Oct 2008
In this paper, the authors examine the area-performance design space of a processing core for a Chip Multiprocessor (CMP), considering both the architectural design space and the tradeoffs of the...
Provided by Stanford University
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White Papers
Programming With Relaxed Streams
Apr 2008
Diminishing returns in single thread performance have forced a reevaluation of priorities in microprocessor design. Recent architectures have foregone deeper pipelining in favor of multiple cores...
Provided by University of Virginia
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White Papers
On-Demand Solution to Minimize I-Cache Leakage Energy With Maintaining Performance
Jul 2007
This paper describes a new on-demand wakeup prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the needed cache line....
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Accelerating Leukocyte Tracking Using CUDA: A Case Study in Leveraging Manycore Coprocessors
May 2009
The availability of easily programmable manycore CPUs and GPUs has motivated investigations into how to best exploit their tremendous computational power for scientific computing. Here the authors...
Provided by University of Virginia
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White Papers
Federation: Boosting Per-Thread Performance of Throughput-Oriented Manycore Architectures
Sep 2010
Manycore architectures designed for parallel workloads are likely to use simple, highly multi-threaded, in-order cores. This maximizes throughput, but only with enough threads to keep hardware...
Provided by Association for Computing Machinery
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White Papers
Accelerating Compute-Intensive Applications With GPUs and FPGAs
Jan 2011
Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are FPGAs and GPUs,...
Provided by University of Virginia
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White Papers
Hierarchical Domain Partitioning for Hierarchical Architectures
Aug 2008
The history of parallel computing shows that good performance is heavily dependent on data locality. Prior knowledge of data access patterns allows for optimizations that reduce data movement,...
Provided by University of Virginia
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White Papers
Federation: Repurposing Scalar Cores for Out-of-Order Instruction Issue
Jun 2008
Future SoCs will contain multiple cores. For workloads with significant parallelism, prior work has shown the benefit of many small, multi-threaded, scalar cores. For workloads that require better...
Provided by Association for Computing Machinery
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White Papers
Predictive Design Space Exploration Using Genetically Programmed Response Surfaces
Jun 2008
Exponential increases in architectural design complexity threaten to make traditional processor design optimization techniques intractable. Genetically Programmed Response Surfaces (GPRS) address...
Provided by Association for Computing Machinery
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White Papers
Performance Modeling and Automatic Ghost Zone Optimization for Iterative Stencil Loops on GPUs
Jun 2009
Iterative Stencil Loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture, there are...
Provided by University of Virginia
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White Papers
Gate-Level Simulation With GPU Computing
Mar 2011
Functional verification of modern digital designs is a crucial, time-consuming task impacting not only the correctness of the final product, but also its time to market. At the heart of most of...
Provided by Association for Computing Machinery
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White Papers
Functional Correctness for CMP Interconnects
Aug 2011
As transistor counts continue to scale, modern designs are transitioning towards large Chip Multi-Processors (CMPs). In order to match the advancing performance of CMPs, on-chip interconnects are...
Provided by University of Michigan
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White Papers
Dynamic Clock Calibration Via Temperature Measurement
Aug 2009
The authors study a clock calibration problem for an ultra-low power timer on a sensor node platform. When the sensor is put into sleep mode, this timer is the only thing left running, so power...
Provided by University of Michigan
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White Papers
An Energy Consumption Model for GPU Computing at Instruction Level
Feb 2012
With the development of hardware and software, GPU has been used in General-Purpose computation field. The high density of computing resource on chip brings in high performance as well as high...
Provided by AICIT
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White Papers
Design of Optimized Fuzzy Logic Controller for Area Minimisation and Its FPGA Implementation
Aug 2010
Area optimization is one of the important problems in reconfigurable systems. A Field-Programmable Gate Array (FPGA) based optimised Fuzzy Logic Controller (FLC) has been developed for speed...
Provided by International Journal of Computer Science and Network Security
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White Papers
Reverse Engineering Utility Functions using Genetic Programming to Detect Anomalous Behavior in Software
Aug 2010
Recent studies have shown the promise of using utility functions to detect anomalous behavior in software systems at runtime. However, it remains a challenge for software engineers to hand-craft a...
Provided by Drexel University
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White Papers
Proposal for Ground Shipping High Volume of Data Parameter in Supersampling Unmanned Aircraft Through Radio Modem
Oct 2011
In an unmanned aircraft, large volumes of data are generated by the various sensors installed on the aircraft. At critical moments such as take-off, landing, parachute openings, or when the...
Provided by IARIA
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White Papers
Rate-Range for an FH-FSK Acoustic Modem
Sep 2007
Signals transmitted through underwater channels experience attenuation due to dissipation of acoustic energy by spreading as well as by absorption. The path loss due to absorption is found to be...
Provided by Association for Computing Machinery
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White Papers
Energy-Efficient Hardware Data Prefetching
Feb 2011
Extensive research has been done in prefetching techniques that hide memory latency in microprocessors leading to performance improvements. However, the energy aspect of prefetching is relatively...
Provided by Institute of Electrical & Electronic Engineers
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White Papers
Design and Optimization of Full Comparator Based on Quantum-Dot Cellular Automata
Apr 2012
Quantum-dot Cellular Automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power...
Provided by ETRI Journal
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White Papers
Optimization of N-Queens Solvers on Graphics Processors
Sep 2011
While Graphics Processing Units (GPUs) show high performance for problems with regular structures, they do not perform well for irregular tasks due to the mismatches between irregular problem...
Provided by Springer Science+Business Media
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White Papers
Transparent, Lightweight Application Execution Replay on Commodity Multiprocessor Operating Systems
Jun 2010
The authors present Scribe, the first system to provide transparent, low-overhead application record-replay and the ability to go live from replayed execution. Scribe introduces new lightweight...
Provided by Association for Computing Machinery
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White Papers
Reliability-Driven Energy-Efficient Task Scheduling for Multiprocessor Real-Time Systems
Oct 2011
This paper proposes a reliability-driven task scheduling scheme for multiprocessor real-time embedded systems that optimizes system energy consumption under stochastic fault occurrences. The task...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
R-BATCH: Task Partitioning for Fault-Tolerant Multiprocessor Real-Time Systems
Apr 2011
Many emerging embedded real-time applications such as SCADA (Supervisory Control And Data Acquisition), autonomous vehicles and advanced avionics, require a high degree of dependability. Dealing...
Provided by Carnegie Mellon University
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White Papers
Energy-Aware Partitioned Fixed-Priority Scheduling for Chip Multi-Processors
Sep 2011
Energy management is becoming an increasingly important problem in application domains ranging from embedded devices to data centers. In many such systems, multi-core processors are projected as a...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
PCOMPATS: Period-Compatible Task Allocation and Splitting on Multi-Core Processors
Jan 2012
Extensive research is underway to build chips with potentially hundreds of cores. In this paper, the authors consider the problem of scheduling periodic real-time tasks on multi-core processors....
Provided by Carnegie Mellon University
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White Papers
SAFER: System-Level Architecture for Failure Evasion in Real-Time Applications
Mar 2012
The authors propose a layer called SAFER (System-level Architecture for Failure Evasion in Real-time applications) to incorporate configurable task-level fault-tolerance features such as Hot...
Provided by Carnegie Mellon University
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White Papers
Leveraging Core Specialization Via OS Scheduling to Improve Performance on Asymmetric Multicore Systems
Apr 2012
Asymmetric Multicore Processors (AMPs) consist of cores with the same ISA (instruction-set architecture), but different micro-architectural features, speed, and power consumption. Because cores...
Provided by Association for Computing Machinery
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White Papers
Effect of Thread Level Parallelism on the Performance of Optimum Architecture for Embedded Applications
Mar 2012
According to the increasing complexity of network application and internet traffic, network processor as a subset of embedded processors have to process more computation intensive tasks. By...
Provided by Academy & Industry Research Collaboration Center
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White Papers
FPGA Real Time Acceleration for Discrete Wavelet Transform of the 5/3 Filter for JPEG2000 Standard
Mar 2012
In recent years video and image compression have became very required. The availability of powerful software design tools is a fundamental requirement to take advantage of the many advanced and...
Provided by Academy & Industry Research Collaboration Center
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White Papers
Drop the Phone and Talk to the Physical World: Programming the Internet of Things With Erlang
Mar 2012
The authors present ELIOT, an Erlang-based development framework expressly conceived for heterogeneous and massively decentralized sensing/actuation systems: a vision commonly regarded as the...
Provided by Politecnico di Milano
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White Papers
Fault-Tolerant Distributed Deployment of Embedded Control Software
May 2008
Safety-critical feedback-control applications may suffer faults in the controlled plant as well as in the execution platform, i.e., the controller. Control theorists design the control laws to be...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Composing Heterogeneous Reactive Systems
Jul 2008
The authors present a compositional theory of heterogeneous reactive systems. The approach is based on the concept of tags marking the events of the signals of a system. Tags can be used for...
Provided by Association for Computing Machinery
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White Papers
A Heterogeneous Parallel System Running Open MPI on a Broadband Network of Embedded Set-Top Devices
May 2010
The authors present a heterogeneous parallel computing system that combines a traditional computer cluster with a broadband network of embedded Set-Top Box (STB) devices. As Multiple Service...
Provided by Association for Computing Machinery
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White Papers
On-Chip Photonic Communication for High-Performance Multi-Core Processors
Oct 2008
The quest for high-performance and low-power has brought computer architects to design multi-core architectures where an increasing number of parallel processing cores are integrated on a single...
Provided by Columbia University
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White Papers
Photonic Many-Core Architecture Study
May 2008
Several recent device technology developments have been fundamentally changing the microprocessor architecture design space. These developments include photonic interconnects, feature size...
Provided by University of California
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White Papers
Time-Division-Multiplexed Arbitration in Silicon Nan photonic Networks-on-Chip for High-Performance Chip Multiprocessors
Oct 2010
As the computational performance of microprocessors continues to grow through the integration of an increasing number of processing cores on a single die, the interconnection network has become...
Provided by Reed Elsevier
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White Papers
A Methodology for Constraint-Driven Synthesis of On-Chip Communications
Mar 2009
The authors present a methodology and an optimization framework for the synthesis of on-chip communication through the assembly of components such as interfaces, routers, buses and links, from a...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Distributed Flit-Buffer Flow Control for Networks-on-Chip
Oct 2008
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for Networks-on-Chip (NoC). Since they both rely on backpressure, the two techniques...
Provided by Association for Computing Machinery
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White Papers
CTC: An End-to-End Flow Control Protocol for Multi-Core Systems-on-Chip
May 2009
The authors propose Connection Then Credits (CTC) as a new end-to-end flow control protocol to handle message-dependent deadlocks in Networks-on-Chip (NoC) for multi-core systems-on-chip. CTC is...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits With Clock Networks
Jun 2011
Analyzing timing yield under process variations is difficult because of the presence of correlations. Reconvergent Fan-Out Nodes (RFONs) within combinational subcircuits are a major source of...
Provided by World Scientific Publishing
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White Papers
Formal Semantics and Analysis of Behavioral AADL Models in Real-Time Maude
Feb 2010
AADL is a standard for modeling embedded systems that is widely used in avionics and other safety-critical applications. However, the AADL standard lacks at present a formal semantics, and this...
Provided by University of Oslo
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White Papers
High Speed and Low Power Dynamic Latched Comparator for PTL Circuit Applications
Jan 2012
Comparators are basic building blocks for designing modern mixed signal systems. Speed and resolution are two important factors which are required for high speed applications. This paper presents...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
Design and Implementation of Pipelined 32-Bit Advanced RISC Processor for Various D.S.P Applications
Jan 2012
In this paper, the authors propose 32-bit pipelined RISC processor using VLIW architectures. This processor is especially used for both D.S.P applications and general purpose applications. Reduced...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
Integrating Logic Analyzer Functionality Into VHDL Designs
Jan 2012
A combined hardware and software system for the debugging of FPGA designs is designed. It provides a powerful logic analyzer implemented as a fully parameterized VHDL description. The system can...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
Implementation of Area Efficient Memory-Based FIR Digital Filter Using LUT-Multiplier
Mar 2012
Memory based structures are well-suited for many Digital Signal Processing (DSP) applications, which involve multiplication with a fixed set of coefficients. Memory-based structures are more...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
A Study on the Design of Coaxial Isolator With Filter Circuit
Dec 2011
In this paper, the detailed design of the 1.8 GHz band Y-junction stripline circulator with the low pass filter circuit in the center conductor in order to higher attenuations below value of -30...
Provided by Dongguk University
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White Papers
Real Time Behavior of Data in Distributed Embedded Systems
Nov 2008
Nowadays, most embedded systems become distributed systems structured as a set of communicating components. Therefore, they display a less deterministic global behavior than centralized systems...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Design and Implementation of Non Real Time and Real Time Digital Filters for Audio Signal Processing
May 2011
An analog active filter can not provide a very sharp cut-off for both higher and lower frequency component, while a Digital Signal Processor (DSP) using digital filter effectively reduces the...
Provided by Journal of Computing
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White Papers
Runtime CPU Scheduler Customization Framework for Real Time Operating System
Mar 2012
Most of the embedded systems have real-time requirements about the use of Real-Time Operating Systems able of satisfying the embedded system requirements. So, in embedded application where the...
Provided by International Journal of Computer Technology and Applications
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White Papers
To GPU Synchronize or Not GPU Synchronize?
Mar 2010
The Graphics Processing Unit (GPU) has evolved from being a fixed-function processor with programmable stages into a programmable processor with many fixed-function components that deliver massive...
Provided by Virginia Tech
-
White Papers
Inter-Block GPU Communication Via Fast Barrier Synchronization
Mar 2010
While GPGPU stands for General-Purpose computation on Graphics Processing Units, the lack of explicit support for inter-block communication on the GPU arguably hampers its broader adoption as a...
Provided by Virginia Tech
-
White Papers
On the Robust Mapping of Dynamic Programming Onto a Graphics Processing Unit
Dec 2009
Graphics Processing Units (GPUs) have been widely used to accelerate algorithms that exhibit massive data parallelism or task parallelism. When such parallelism is not inherent in an algorithm,...
Provided by Virginia Tech
-
White Papers
Virtual Hierarchies
Feb 2008
Memory system hierarchies are fundamental to computing systems. They have long improved performance because most programs temporally concentrate accesses to code and data. However, emerging...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Forward flow: A Scalable Core for Power-Constrained CMPs
Apr 2010
Chip MultiProcessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased core per-socket count will...
Provided by Association for Computing Machinery
-
White Papers
Calvin: Deterministic or Not? Free Will to Choose
Dec 2010
Most shared memory systems maximize performance by unpredictably resolving memory races. Unpredictable memory races can lead to non-determinism in parallel programs, which can suffer from...
Provided by University of Wisconsin-Madison
-
White Papers
Two Hardware-Based Approaches for Deterministic Multiprocessor Replay
Jun 2009
Many shared-memory multithreaded executions behave non-deterministically when run on multiprocessor hardware such as emerging multicore systems. Recording nondeterministic events in such...
Provided by Association for Computing Machinery
-
White Papers
Active Storage Revisited: The Case for Power and Performance Benefits for Unstructured Data Processing Applications
May 2008
The proliferation of digital data has resulted in a mushrooming of data-intensive applications, especially in the area of unstructured data processing. Given the growing popularity of unstructured...
Provided by Association for Computing Machinery
-
White Papers
Compiler and Runtime Support for Enabling Generalized Reduction Computations on Heterogeneous Parallel Configurations
Jun 2010
A trend that has materialized, and has given rise to much attention, is of the increasingly heterogeneous computing platforms. Presently, it has become very common for a desktop or a notebook...
Provided by Association for Computing Machinery
-
White Papers
Balancing Soft Error Coverage With Lifetime Reliability in Redundantly Multithreaded Processors
Jun 2009
Silicon reliability is a key challenge facing the micro-processor industry. Processors need to be designed such that they are resilient against both soft errors and lifetime reliability phenomena....
Provided by University of Virginia
-
White Papers
PEEP: Exploiting Predictability of Memory Dependences in SMT Processors
Jan 2008
Simultaneous MultiThreading (SMT) attempts to keep a dynamically scheduled processor's resources busy with work from multiple independent threads. Threads with long-latency stalls, however, can...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
An Evaluation of Hash Functions on a Power Analysis Resistant Processor Architecture
Dec 2010
Cryptographic hash functions are omnipresent components in security-critical software and devices; they support, for example, digital signature and data authenticity schemes, mechanisms for key...
Provided by University of Bristol
-
White Papers
Epoch Parallelism: One Execution Is Not Enough
Sep 2010
The conventional approach for using multiprocessors requires programmers to write correct, scalable parallel programs. Unfortunately, writing such programs remains a daunting task, despite decades...
Provided by University of Michigan
-
White Papers
Runahead Threads to Improve SMT Performance
Apr 2008
In this paper, the authors propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded (SMT)...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect
Apr 2008
In this paper, the authors explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core Network-on-Chip...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Automated Microprocessor Stressmark Generation
Apr 2008
Estimating the maximum power and thermal characteristics of a processor is essential for designing its power delivery system, packaging, cooling, and power/thermal management schemes. Typical...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
An OS-Based Alternative to Full Hardware Coherence on Tiled CMPs
Apr 2008
The interconnect mechanisms (shared bus or crossbar) used in current Chip-Multi Processors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling to a larger...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Gaining Insights Into Multicore Cache Partitioning: Bridging the Gap Between Simulation and Real Systems
Apr 2008
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often has several...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
DeCoR: A Delayed Commit and Rollback Mechanism for Handling Inductive Noise in Processors
Apr 2008
Increases in peak current draw and reductions in the operating voltage of processors stress the importance of dealing with voltage fluctuations in processors. Noise-margin violations lead to...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Speculative Instruction Validation for Performance-Reliability Trade-Off
Apr 2008
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant Multi-Threading (RMT)...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Design and Implementation of the Blue Gene/P Snoop Filter
Jan 2008
As multi-core processors evolve, coherence traffic between cores is becoming problematic, both in terms of performance and power. The negative effects of coherence (snoop) traffic can be...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Digital Rights Enabled Graphics Processing System
Jan 2011
With the emergence of 3D graphics/arts assets commerce on the Internet, to protect their intellectual property and to restrict their usage have become a new design challenge. This paper presents a...
Provided by EUROGRAPHICS Association
-
White Papers
Dynamic Iterations for the Solution of Ordinary Differential Equations on Multicore Processors
Feb 2009
In the past few years, there has been a trend of providing increased computing power through greater number of cores on a chip, rather than through higher clock speeds. In order to exploit the...
Provided by Florida State University
-
White Papers
Optimizing Assignment of Threads to SPEs on the Cell BE Processor
Feb 2009
The Cell is a heterogeneous multicore processor that has attracted much attention in the HPC community. The bulk of the computational workload on the Cell processor is carried by eight...
Provided by Florida State University
-
White Papers
Distributed Estimation and Coding: A Sequential Framework Based on a Side-Informed Decomposition
Feb 2011
The authors propose a sequential framework for the distributed multiple-sensor estimation and coding problem that decomposes the problem into a series of side-informed source coding problems and...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
CellSort: High Performance Sorting on the Cell Processor
Sep 2007
In this paper the authors describe the design and implementation of CellSort a high performance distributed sort algorithm for the Cell processor. They design CellSort as a distributed bitonic...
Provided by Association for Computing Machinery
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White Papers
Adaptive Aggregation on Chip Multiprocessors
Sep 2007
The recent introduction of commodity chip multiprocessors requires that the design of core database operations be care-fully examined to take full advantage of on-chip parallelism. In this paper...
Provided by Association for Computing Machinery
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White Papers
GPU Computing
Oct 2009
The Graphics Processing Unit (GPU) has become an integral part of today's mainstream computing systems. Over the past six years, there has been a marked increase in the performance and...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Area-Efficiency in CMP Core Design: Co-Optimization of Microarchitecture and Physical Design
Oct 2008
In this paper, the authors examine the area-performance design space of a processing core for a Chip Multiprocessor (CMP), considering both the architectural design space and the tradeoffs of the...
Provided by Stanford University
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White Papers
Programming With Relaxed Streams
Apr 2008
Diminishing returns in single thread performance have forced a reevaluation of priorities in microprocessor design. Recent architectures have foregone deeper pipelining in favor of multiple cores...
Provided by University of Virginia
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White Papers
On-Demand Solution to Minimize I-Cache Leakage Energy With Maintaining Performance
Jul 2007
This paper describes a new on-demand wakeup prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the needed cache line....
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Accelerating Leukocyte Tracking Using CUDA: A Case Study in Leveraging Manycore Coprocessors
May 2009
The availability of easily programmable manycore CPUs and GPUs has motivated investigations into how to best exploit their tremendous computational power for scientific computing. Here the authors...
Provided by University of Virginia
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White Papers
Federation: Boosting Per-Thread Performance of Throughput-Oriented Manycore Architectures
Sep 2010
Manycore architectures designed for parallel workloads are likely to use simple, highly multi-threaded, in-order cores. This maximizes throughput, but only with enough threads to keep hardware...
Provided by Association for Computing Machinery
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White Papers
Accelerating Compute-Intensive Applications With GPUs and FPGAs
Jan 2011
Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are FPGAs and GPUs,...
Provided by University of Virginia
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White Papers
Hierarchical Domain Partitioning for Hierarchical Architectures
Aug 2008
The history of parallel computing shows that good performance is heavily dependent on data locality. Prior knowledge of data access patterns allows for optimizations that reduce data movement,...
Provided by University of Virginia
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White Papers
Federation: Repurposing Scalar Cores for Out-of-Order Instruction Issue
Jun 2008
Future SoCs will contain multiple cores. For workloads with significant parallelism, prior work has shown the benefit of many small, multi-threaded, scalar cores. For workloads that require better...
Provided by Association for Computing Machinery
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White Papers
Predictive Design Space Exploration Using Genetically Programmed Response Surfaces
Jun 2008
Exponential increases in architectural design complexity threaten to make traditional processor design optimization techniques intractable. Genetically Programmed Response Surfaces (GPRS) address...
Provided by Association for Computing Machinery
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White Papers
Performance Modeling and Automatic Ghost Zone Optimization for Iterative Stencil Loops on GPUs
Jun 2009
Iterative Stencil Loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture, there are...
Provided by University of Virginia
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White Papers
Exploiting Inter-Thread Temporal Locality for Chip Multithreading
Feb 2010
Multi-core organizations increasingly support multiple threads per core. Threads on a core usually share a single first-level data cache, so thread schedulers must try to minimize cache contention...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A Performance Study for Iterative Stencil Loops on GPUs With Ghost Zone Optimizations
Jun 2010
Iterative Stencil Loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture, there are...
Provided by University of Virginia
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