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Mission Statement
TechRepublic's ITPapers is the Web's largest library of free technical IT white papers, webcasts, and case studies. Covering IT categories including Data Management, IT Management, Networking, Communications, Enterprise Applications, Storage, Security and much more, TechRepublic's White Paper Directory is the best source for technical white papers and IT information.
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White Papers
Distributed Estimation and Coding: A Sequential Framework Based on a Side-Informed Decomposition
Feb 2011
The authors propose a sequential framework for the distributed multiple-sensor estimation and coding problem that decomposes the problem into a series of side-informed source coding problems and...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
CellSort: High Performance Sorting on the Cell Processor
Sep 2007
In this paper the authors describe the design and implementation of CellSort a high performance distributed sort algorithm for the Cell processor. They design CellSort as a distributed bitonic...
Provided by Association for Computing Machinery
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White Papers
Adaptive Aggregation on Chip Multiprocessors
Sep 2007
The recent introduction of commodity chip multiprocessors requires that the design of core database operations be care-fully examined to take full advantage of on-chip parallelism. In this paper...
Provided by Association for Computing Machinery
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White Papers
GPU Computing
Oct 2009
The Graphics Processing Unit (GPU) has become an integral part of today's mainstream computing systems. Over the past six years, there has been a marked increase in the performance and...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Area-Efficiency in CMP Core Design: Co-Optimization of Microarchitecture and Physical Design
Oct 2008
In this paper, the authors examine the area-performance design space of a processing core for a Chip Multiprocessor (CMP), considering both the architectural design space and the tradeoffs of the...
Provided by Stanford University
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White Papers
Programming With Relaxed Streams
Apr 2008
Diminishing returns in single thread performance have forced a reevaluation of priorities in microprocessor design. Recent architectures have foregone deeper pipelining in favor of multiple cores...
Provided by University of Virginia
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White Papers
On-Demand Solution to Minimize I-Cache Leakage Energy With Maintaining Performance
Jul 2007
This paper describes a new on-demand wakeup prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the needed cache line....
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Accelerating Leukocyte Tracking Using CUDA: A Case Study in Leveraging Manycore Coprocessors
May 2009
The availability of easily programmable manycore CPUs and GPUs has motivated investigations into how to best exploit their tremendous computational power for scientific computing. Here the authors...
Provided by University of Virginia
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White Papers
Federation: Boosting Per-Thread Performance of Throughput-Oriented Manycore Architectures
Sep 2010
Manycore architectures designed for parallel workloads are likely to use simple, highly multi-threaded, in-order cores. This maximizes throughput, but only with enough threads to keep hardware...
Provided by Association for Computing Machinery
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White Papers
Accelerating Compute-Intensive Applications With GPUs and FPGAs
Jan 2011
Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are FPGAs and GPUs,...
Provided by University of Virginia
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White Papers
Hierarchical Domain Partitioning for Hierarchical Architectures
Aug 2008
The history of parallel computing shows that good performance is heavily dependent on data locality. Prior knowledge of data access patterns allows for optimizations that reduce data movement,...
Provided by University of Virginia
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White Papers
Federation: Repurposing Scalar Cores for Out-of-Order Instruction Issue
Jun 2008
Future SoCs will contain multiple cores. For workloads with significant parallelism, prior work has shown the benefit of many small, multi-threaded, scalar cores. For workloads that require better...
Provided by Association for Computing Machinery
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White Papers
Predictive Design Space Exploration Using Genetically Programmed Response Surfaces
Jun 2008
Exponential increases in architectural design complexity threaten to make traditional processor design optimization techniques intractable. Genetically Programmed Response Surfaces (GPRS) address...
Provided by Association for Computing Machinery
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White Papers
Performance Modeling and Automatic Ghost Zone Optimization for Iterative Stencil Loops on GPUs
Jun 2009
Iterative Stencil Loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture, there are...
Provided by University of Virginia
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White Papers
Exploiting Inter-Thread Temporal Locality for Chip Multithreading
Feb 2010
Multi-core organizations increasingly support multiple threads per core. Threads on a core usually share a single first-level data cache, so thread schedulers must try to minimize cache contention...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A Performance Study for Iterative Stencil Loops on GPUs With Ghost Zone Optimizations
Jun 2010
Iterative Stencil Loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture, there are...
Provided by University of Virginia
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White Papers
Differentiating the Roles of IR Measurement and Simulation for Power and Temperature-Aware Design
Oct 2009
In temperature-aware design, the presence or absence of a heatsink fundamentally changes the thermal behavior with important design implications. In recent years, chip-level InfraRed (IR) thermal...
Provided by University of Virginia
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White Papers
Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model
Apr 2008
Preventing silicon chips from negative, even disastrous thermal hazards has become increasingly challenging these days; considering thermal effects early in the design cycle is thus required. To...
Provided by University of Virginia
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White Papers
Accurate Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model
Aug 2008
Preventing silicon chips from negative, even disastrous thermal hazards has become increasingly challenging these days; Considering thermal effects early in the design cycle is thus required. To...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Enabling Task Parallelism in the CUDA Scheduler
Jul 2009
General purpose computing on Graphics Processing Units (GPUs) introduces the challenge of scheduling independent tasks on devices designed for data parallel or SPMD applications. This paper...
Provided by University of Virginia
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White Papers
Many-Core Design From a Thermal Perspective
Jun 2008
Air cooling limits have been a major design challenge in recent years for integrated circuits. Multi-core exacerbates thermal challenges because power scales with the number of cores, but also...
Provided by Association for Computing Machinery
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White Papers
Increasing Memory Miss Tolerance for SIMD Cores
Aug 2009
Manycore processors with wide SIMD cores are becoming a popular choice for the next generation of throughput oriented architectures. The authors introduce a hardware technique called "Diverge on...
Provided by Association for Computing Machinery
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White Papers
Thermal Modeling and Management of Microprocessors
May 2009
The most recent, and arguably one of the most difficult obstacles to the exponential growth in transistor density predicted by Moore's Law is that of removing the large amount of heat generated...
Provided by University of Virginia
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White Papers
Integrating Utilization Control With Task Consolidation for Power Optimization in Multi-Core Real-Time Systems
Oct 2010
Since multi-core processors have become a primary trend in processor development, new scheduling algorithms are needed to minimize power consumption while achieving the desired timeliness...
Provided by University of Tennessee
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White Papers
Hierarchical Utilization Control for Real-Time and Resilient Power Grid
Dec 2009
Blackouts in the daily life can be disastrous with enormous economic loss. Blackouts usually occur when appropriate corrective actions are not effectively taken for an initial contingency,...
Provided by University of Tennessee
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White Papers
On Controllability and Feasibility of Utilization Control in Distributed Real-Time Systems
Dec 2009
Feedback control techniques have recently been applied to a variety of real-time systems. However, a fundamental issue that was left out is guaranteeing system controllability and the feasibility...
Provided by University of Tennessee
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White Papers
Comparative Analysis of Neural Network Techniques Vs Statistical Methods in Capacity Planning
Aug 2007
Capacity planning is a technique which can be used to predict the computing resource needs of an organization for the future after studying current usage patterns. This is of special import for...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Achieving Fair or Differentiated Cache Sharing in Power-Constrained Chip Multiprocessors
Sep 2009
Limiting the peak power consumption of Chip Multi Processors (CMPs) has recently received a lot of attention. In order to enable chip-level power capping, the peak power consumption of on-chip L2...
Provided by University of Tennessee
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White Papers
Temperature-Constrained Power Control for Chip Multiprocessors With Online Model Estimation
Jun 2009
As Chip Multiprocessors (CMPs) become the main trend in processor development, various power and thermal management strategies have recently been proposed to optimize system performance while...
Provided by Association for Computing Machinery
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White Papers
Power-Aware CPU Utilization Control for Distributed Real-Time Systems
Dec 2009
CPU utilization control has recently been demonstrated to be an effective way of meeting end-to-end deadlines for distributed real-time systems running in unpredictable environments. However,...
Provided by University of Tennessee
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White Papers
Dynamic Thermal and Timeliness Guarantees for Distributed Real-Time Embedded Systems
Jun 2010
Distributed real-time embedded systems have stringent requirements for key performance properties, such as end-to-end timeliness and reliability, in order to operate properly. In recent years,...
Provided by University of Tennessee
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White Papers
Cache-Aware Utilization Control for Energy-Efficient Multi-Core Real-Time Systems
Oct 2010
Multi-core processors are anticipated to become a major development platform for real-time systems. However, existing power management algorithms are not designed to sufficiently utilize the...
Provided by University of Tennessee
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White Papers
Dynamic Power Partitioning and Control for Performance Optimization in Chip Multiprocessors
Nov 2009
Since power consumption has become a major constraint for the further throughput improvement of Chip MultiProcessors (CMPs), a key challenge is to optimize the performance of a CMP within a power...
Provided by University of Tennessee
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White Papers
PAUC: Power-Aware Utilization Control in Distributed Real-Time Systems
Aug 2010
CPU utilization control has recently been demonstrated to be an effective way of meeting end-to-end deadlines for distributed real-time systems running in unpredictable environments. However,...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Achieving Bounded Matching Delay and Maximized Throughput in Information Dissemination Management
Jan 2011
The demand for high performance information dissemination is increasing in many applications, such as ecommerce and security alerting systems. These applications usually require that the desired...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
DEUCON: Decentralized End-to-End Utilization Control for Distributed Real-Time Systems
Jul 2007
Many real-time systems must control their CPU utilizations in order to meet end-to-end deadlines and prevent overload. Utilization control is particularly challenging in distributed real-time...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Adaptive Power Control With Online Model Estimation for Chip Multiprocessors
Oct 2010
As Chip Multiprocessors (CMPs) become the main trend in processor development, various power and thermal management strategies have recently been proposed to optimize system performance while...
Provided by University of Tennessee
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White Papers
A Low-Power Globally Synchronous Locally Asynchronous FFT Processor
Sep 2007
Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to efficient in order to achieve...
Provided by Springer Science+Business Media
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White Papers
Performance Evaluation of View-Oriented Parallel Programming on Cluster of Computers
Sep 2007
View-Oriented Parallel Programming(VOPP) is a novel programming style based on Distributed Shared Memory, which is friendly and easy for programmers to use. In this paper the authors compare VOPP...
Provided by Springer Science+Business Media
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White Papers
Parallel Genetic Algorithms for DVS Scheduling of Distributed Embedded Systems
Sep 2007
Many of today's embedded systems, such as wireless and portable devices rely heavily on the limited power supply. Therefore, energy efficiency becomes one of the major design concerns for embedded...
Provided by Springer Science+Business Media
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White Papers
A Study on the Design of Coaxial Isolator With Filter Circuit
Dec 2011
In this paper, the detailed design of the 1.8 GHz band Y-junction stripline circulator with the low pass filter circuit in the center conductor in order to higher attenuations below value of -30...
Provided by Dongguk University
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White Papers
Real Time Behavior of Data in Distributed Embedded Systems
Nov 2008
Nowadays, most embedded systems become distributed systems structured as a set of communicating components. Therefore, they display a less deterministic global behavior than centralized systems...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Design and Implementation of Non Real Time and Real Time Digital Filters for Audio Signal Processing
May 2011
An analog active filter can not provide a very sharp cut-off for both higher and lower frequency component, while a Digital Signal Processor (DSP) using digital filter effectively reduces the...
Provided by Journal of Computing
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White Papers
Runtime CPU Scheduler Customization Framework for Real Time Operating System
Mar 2012
Most of the embedded systems have real-time requirements about the use of Real-Time Operating Systems able of satisfying the embedded system requirements. So, in embedded application where the...
Provided by International Journal of Computer Technology and Applications
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White Papers
Blocking Misbehaving Users In Anonymizying Networks- Embedded Based
Mar 2012
Anonymizing networks such as Tor allow users to access Internet services privately by using a series of routers to hide the client's IP address from the server. The success of such networks,...
Provided by International Journal of Power Control Signal and Computation (IJPCSC)
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White Papers
VLSI Implementation of Fast Convolution Based 2-D Discrete Wavelet Transform for High Speed, Area Efficient Image Computing
Mar 2012
A VLSI design approach of a high speed and real-time 2-D Discrete Wavelet Transform computing is being presented in the paper. The proposed architecture, based on new and fast convolution...
Provided by International Journal of Power Control Signal and Computation (IJPCSC)
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White Papers
An Optimized Scaled Neural Branch Predictor
Oct 2011
Conditional branch prediction remains one of the most important enabling technologies for high-performance microprocessors. A small improvement in accuracy can result in a large improvement in...
Provided by University of Texas
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White Papers
Program Interferometry
Nov 2011
Modern microprocessors have many micro-architectural features. Quantifying the performance impact of one feature such as dynamic branch prediction can be difficult. On one hand, a timing simulator...
Provided by University of Texas
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White Papers
Design and Implementation of Adder and Subtracter Experiments Using Virtual Intelligent SoftLab
Jan 2012
The scope of this paper includes study and implementation of Full Adder and Subtractor. A full-adder and Subtracter is composed with IC and virtual instruments. Along with the VIS model the...
Provided by International Journal of Computer Science and Telecommunications
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White Papers
Energy-Aware Task Partitioning on Heterogeneous Multiprocessor Platforms
Mar 2012
Efficient task partitioning plays a crucial role in achieving high performance at multiprocessor platforms. This paper addresses the problem of energy-aware static partitioning of periodic...
Provided by International Journal of Computer Science Issues
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White Papers
Digital Logic Embedding Using Single Row
Dec 2011
The authors present a technique to improve embedding capacity of Image using digital logic in this paper. They have applied digital logic operations on two equal halves of an image row to derive...
Provided by Engg Journals Publications
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White Papers
Task Scheduling Algorithm to Reduce the Number of Processors Using Merge Conditions
Feb 2012
Some task scheduling algorithms generate the shortest schedule, when its input DAG satisfies a specified condition. Among those scheduling algorithms, TDS algorithm proposed a DAG condition where...
Provided by Engg Journals Publications
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White Papers
Identification of Highly Jittered Radar Emitters: Issues on Low Cost Embedded Design
Feb 2012
This paper presents efforts toward design of radar identification system for highly jittered radar emitters. The paper first provides a mathematical background of clustering techniques, and then...
Provided by The Second International Conference on Communications and Information Technology
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White Papers
Performance Evaluation of a Simplified Matrix Processor
Feb 2012
Data parallel applications are growing in importance and demanding increased performance from hardware. Since, the fundamental data structures for a wide variety of data-parallel applications are...
Provided by The Second International Conference on Communications and Information Technology
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White Papers
Performance Evaluation of a 16.16 Fixed-Point Multiplier Implemented on the FALCON-A Processor
Feb 2012
This paper describes the implementation of a fixed point multiplier (using the 16.16 format) on the FALCON-A processor. Special assembly language coding techniques have been used to achieve the...
Provided by The Second International Conference on Communications and Information Technology
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White Papers
Implementation and Control Different Multilevel Inverter Topologies for Current Waveform Improvement
Mar 2012
Multilevel converters offer advantages in terms of the output waveform quality due to the increased number of levels used in the output voltage modulation. This advantage is particularly true for...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Improved Direct Torque Control of Induction Motor Using Fuzzy Logic Based Duty Ratio Controller
Nov 2011
Classical DTC has inherent disadvantages such as: problems during starting resulting from the null states, the compulsory requirement of torque and flux estimators, and torque ripple. In this...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Issues in Caching Techniques to Improve System Performance in Chip Multiprocessors
Nov 2011
As cache management in chip multiprocessors has become more critical because of the diverse workloads, increasing working sets of many emerging applications, increasing memory latency and...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Design and Simulation of an Intelligent Traffic Control System
Nov 2011
This paper described the authors' research experiences of building an intelligent system to monitor and control road traffic in a Nigerian city. A hybrid methodology obtained by the crossing of...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
LFSR Test Pattern for Fault Detection and Diagnosis for FPGA CLB Cells
Mar 2012
The increasing growth of sub-micron technology has resulted in the difficulty of VLSI testing. Test and design for testability are recognized today as critical to a successful design. Field...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Efficient Implementations of Discrete Wavelet Transforms Using FPGAs
Sep 2011
Recently, the Wavelet Transform has gained a lot of popularity in the field of signal and image processing. This is due to its capability of providing both time and frequency information...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Analog Integrated Circuit Design and Testing Using the Field Programmable Analog Array Technology
Sep 2011
Due to their reliability, performance and rapid prototyping, programmable logic devices overcome the use of ASICs in the digital system design. However, the similar solution for analog signals was...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Design and Analysis of a Fault Tolerant Microprocessor Based on Triple Modular Redundancy Using VHDL
Mar 2011
There are numerous real time & operation critical systems in which the failure of the system is unacceptable at any stage of processing. The examples of such systems are like ATM machines,...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Embedded Intelligent Sensor for Conveyer Belt-Fuzzy System Application
Mar 2011
A conveyor belt includes at least one rip detection sensor, one position detection sensor and a speed measurement sensor. In this paper, a complete sensor solution for the industrial conveyer belt...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Strategies & Methodologies for Low Power VLSI Designs: A Review
May 2011
Low power has emerged as a principal theme in today's world of electronics industries. Power dissipation has become an important consideration as performance and area for VLSI Chip design. With...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Implementation of User Interface for Microprocessor Trainer
Aug 2011
This paper aims to design and construct the microcontroller-based user interface system and to study input, computation, and output for microprocessor trainer. The other two activities beyond...
Provided by University of Computer Studies
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White Papers
Compact Implementation of Threefish and Skein on FPGA
Mar 2012
The SHA-3 finalist Skein is built from the tweakable Threefish block cipher. In order to have a better understanding of the computational efficiency of Skein (resource sharing, memory access...
Provided by Anadolu University
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White Papers
Design of Cache Controller for Multi-Core Processor System
Apr 2012
To meet the growing needs of computing power, communication speed and performance requirements demanded by today's applications, processor clock speed has to be increased. However, increasing...
Provided by G.H. Raisoni College of Engineering
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White Papers
Groestl Tweaks and Their Effect on FPGA Results
Nov 2011
The authors have performed the first order analysis of the influence of the Round 3 tweaks in Groestl on the performance of this algorithm in FPGAs. Both Groestl-0 and the revised Groestl have...
Provided by George Mason University
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White Papers
Random Number Generation Based on Oscillatory Metastability in Ring Circuits
Nov 2011
Random number generator designs are discussed, which utilize oscillatory metastability, induced by switching between two stable states of ring-connected digital gates. For a short time after the...
Provided by International Association for Cryptologic Research
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White Papers
Collision for 75-Step SHA-1: Intensive Parallelization With GPU
Nov 2011
The authors present a brief report on the collision search for the reduced SHA-1. With a few improvements to their previous work, directed at efficient parallelization on a GPU cluster, they...
Provided by International Association for Cryptologic Research
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White Papers
SHA-3 on ARM11 Processors
Nov 2011
This paper presents high-speed assembly implementations of the 256-bit-output versions of all five SHA-3 finalists and of SHA-256 for the ARM11 family of processors. The authors report new speed...
Provided by National Taiwan University
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White Papers
Using Shared Library Interposing for Transparent Application Acceleration in Systems With Heterogeneous Hardware Accelerators
Jul 2010
Today's computer systems increasingly comprise heterogeneous computing elements like multi-core processors, graphics processing units, and specialized co-processors, which allow parallel...
Provided by University of Paderborn
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White Papers
Direct N-Body Kernels for Multicore Platforms
Jun 2010
The authors present an inter-architectural comparison of single- and double-precision direct n-body implementations on modern multi-core platforms, including those based on the Intel Nehalem and...
Provided by Georgia Institute of Technology
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White Papers
Model-Driven Autotuning of Sparse Matrix-Vector Multiply on GPUs
Jan 2010
The authors present a performance model-driven framework for automated performance tuning (auto-tuning) of Sparse Matrix-Vector multiply (SpMV) on systems accelerated by Graphics Processing Units...
Provided by Association for Computing Machinery
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White Papers
On the Limits of GPU Acceleration
May 2010
This paper throws a small "Wet blanket" on the hot topic of GPGPU acceleration, based on experience analyzing and tuning both multithreaded CPU and GPU implementations of three computations in...
Provided by Georgia Institute of Technology
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White Papers
Optimum Body Biasing Technique in Domino Logic Gate Design for Low Power Applications
Dec 2011
Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. These dynamic...
Provided by International Journal of Computer Applications
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White Papers
Reconfigurable Network on Chip Router for Image Processing Based Multiprocessor Applications
Dec 2011
Real time Image Processing (I.P) systems, involving on board multiprocessor communication, use standard bus based communication. The load on the system to deliver the output towards real time...
Provided by International Journal of Computer Applications
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White Papers
A Fast Timing-Accurate MPSoC HW/SW Co-Simulation Platform Based on a Novel Synchronization Scheme
Mar 2010
Fast and accurate full-system simulation is needed for MPSoC design space exploration to achieve tight time-to-market design goals. In the field of full-system simulation, transaction level...
Provided by Harbin Institute of Technology
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White Papers
Computing Worst Case Execution Time by Symbolically Executing a Time-Accurate Hardware Model
Jun 2011
To ensure that a program will respect all its timing constraints the authors must be able to compute a safe estimation of its Worst Case Execution Time (WCET). However, with the increasing...
Provided by ENSTA-École Nationale Supérieure de Techniques Avancées
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White Papers
Adaptive Aggregation on Chip Multiprocessors
Sep 2007
The recent introduction of commodity chip multiprocessors requires that the design of core database operations be care-fully examined to take full advantage of on-chip parallelism. In this paper...
Provided by Association for Computing Machinery
-
White Papers
GPU Computing
Oct 2009
The Graphics Processing Unit (GPU) has become an integral part of today's mainstream computing systems. Over the past six years, there has been a marked increase in the performance and...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Area-Efficiency in CMP Core Design: Co-Optimization of Microarchitecture and Physical Design
Oct 2008
In this paper, the authors examine the area-performance design space of a processing core for a Chip Multiprocessor (CMP), considering both the architectural design space and the tradeoffs of the...
Provided by Stanford University
-
White Papers
Programming With Relaxed Streams
Apr 2008
Diminishing returns in single thread performance have forced a reevaluation of priorities in microprocessor design. Recent architectures have foregone deeper pipelining in favor of multiple cores...
Provided by University of Virginia
-
White Papers
On-Demand Solution to Minimize I-Cache Leakage Energy With Maintaining Performance
Jul 2007
This paper describes a new on-demand wakeup prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the needed cache line....
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Accelerating Leukocyte Tracking Using CUDA: A Case Study in Leveraging Manycore Coprocessors
May 2009
The availability of easily programmable manycore CPUs and GPUs has motivated investigations into how to best exploit their tremendous computational power for scientific computing. Here the authors...
Provided by University of Virginia
-
White Papers
Federation: Boosting Per-Thread Performance of Throughput-Oriented Manycore Architectures
Sep 2010
Manycore architectures designed for parallel workloads are likely to use simple, highly multi-threaded, in-order cores. This maximizes throughput, but only with enough threads to keep hardware...
Provided by Association for Computing Machinery
-
White Papers
Accelerating Compute-Intensive Applications With GPUs and FPGAs
Jan 2011
Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are FPGAs and GPUs,...
Provided by University of Virginia
-
White Papers
Hierarchical Domain Partitioning for Hierarchical Architectures
Aug 2008
The history of parallel computing shows that good performance is heavily dependent on data locality. Prior knowledge of data access patterns allows for optimizations that reduce data movement,...
Provided by University of Virginia
-
White Papers
Federation: Repurposing Scalar Cores for Out-of-Order Instruction Issue
Jun 2008
Future SoCs will contain multiple cores. For workloads with significant parallelism, prior work has shown the benefit of many small, multi-threaded, scalar cores. For workloads that require better...
Provided by Association for Computing Machinery
-
White Papers
Predictive Design Space Exploration Using Genetically Programmed Response Surfaces
Jun 2008
Exponential increases in architectural design complexity threaten to make traditional processor design optimization techniques intractable. Genetically Programmed Response Surfaces (GPRS) address...
Provided by Association for Computing Machinery
-
White Papers
Performance Modeling and Automatic Ghost Zone Optimization for Iterative Stencil Loops on GPUs
Jun 2009
Iterative Stencil Loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture, there are...
Provided by University of Virginia
-
White Papers
Exploiting Inter-Thread Temporal Locality for Chip Multithreading
Feb 2010
Multi-core organizations increasingly support multiple threads per core. Threads on a core usually share a single first-level data cache, so thread schedulers must try to minimize cache contention...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Performance Study for Iterative Stencil Loops on GPUs With Ghost Zone Optimizations
Jun 2010
Iterative Stencil Loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture, there are...
Provided by University of Virginia
-
White Papers
Differentiating the Roles of IR Measurement and Simulation for Power and Temperature-Aware Design
Oct 2009
In temperature-aware design, the presence or absence of a heatsink fundamentally changes the thermal behavior with important design implications. In recent years, chip-level InfraRed (IR) thermal...
Provided by University of Virginia
-
White Papers
Accurate, Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model
Apr 2008
Preventing silicon chips from negative, even disastrous thermal hazards has become increasingly challenging these days; considering thermal effects early in the design cycle is thus required. To...
Provided by University of Virginia
-
White Papers
Accurate Pre-RTL Temperature-Aware Design Using a Parameterized, Geometric Thermal Model
Aug 2008
Preventing silicon chips from negative, even disastrous thermal hazards has become increasingly challenging these days; Considering thermal effects early in the design cycle is thus required. To...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Enabling Task Parallelism in the CUDA Scheduler
Jul 2009
General purpose computing on Graphics Processing Units (GPUs) introduces the challenge of scheduling independent tasks on devices designed for data parallel or SPMD applications. This paper...
Provided by University of Virginia
-
White Papers
Many-Core Design From a Thermal Perspective
Jun 2008
Air cooling limits have been a major design challenge in recent years for integrated circuits. Multi-core exacerbates thermal challenges because power scales with the number of cores, but also...
Provided by Association for Computing Machinery
-
White Papers
Increasing Memory Miss Tolerance for SIMD Cores
Aug 2009
Manycore processors with wide SIMD cores are becoming a popular choice for the next generation of throughput oriented architectures. The authors introduce a hardware technique called "Diverge on...
Provided by Association for Computing Machinery
-
White Papers
Thermal Modeling and Management of Microprocessors
May 2009
The most recent, and arguably one of the most difficult obstacles to the exponential growth in transistor density predicted by Moore's Law is that of removing the large amount of heat generated...
Provided by University of Virginia
-
White Papers
Integrating Utilization Control With Task Consolidation for Power Optimization in Multi-Core Real-Time Systems
Oct 2010
Since multi-core processors have become a primary trend in processor development, new scheduling algorithms are needed to minimize power consumption while achieving the desired timeliness...
Provided by University of Tennessee
-
White Papers
Hierarchical Utilization Control for Real-Time and Resilient Power Grid
Dec 2009
Blackouts in the daily life can be disastrous with enormous economic loss. Blackouts usually occur when appropriate corrective actions are not effectively taken for an initial contingency,...
Provided by University of Tennessee
-
White Papers
On Controllability and Feasibility of Utilization Control in Distributed Real-Time Systems
Dec 2009
Feedback control techniques have recently been applied to a variety of real-time systems. However, a fundamental issue that was left out is guaranteeing system controllability and the feasibility...
Provided by University of Tennessee
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White Papers
Comparative Analysis of Neural Network Techniques Vs Statistical Methods in Capacity Planning
Aug 2007
Capacity planning is a technique which can be used to predict the computing resource needs of an organization for the future after studying current usage patterns. This is of special import for...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Achieving Fair or Differentiated Cache Sharing in Power-Constrained Chip Multiprocessors
Sep 2009
Limiting the peak power consumption of Chip Multi Processors (CMPs) has recently received a lot of attention. In order to enable chip-level power capping, the peak power consumption of on-chip L2...
Provided by University of Tennessee
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White Papers
Temperature-Constrained Power Control for Chip Multiprocessors With Online Model Estimation
Jun 2009
As Chip Multiprocessors (CMPs) become the main trend in processor development, various power and thermal management strategies have recently been proposed to optimize system performance while...
Provided by Association for Computing Machinery
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White Papers
Power-Aware CPU Utilization Control for Distributed Real-Time Systems
Dec 2009
CPU utilization control has recently been demonstrated to be an effective way of meeting end-to-end deadlines for distributed real-time systems running in unpredictable environments. However,...
Provided by University of Tennessee
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White Papers
Dynamic Thermal and Timeliness Guarantees for Distributed Real-Time Embedded Systems
Jun 2010
Distributed real-time embedded systems have stringent requirements for key performance properties, such as end-to-end timeliness and reliability, in order to operate properly. In recent years,...
Provided by University of Tennessee
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White Papers
Cache-Aware Utilization Control for Energy-Efficient Multi-Core Real-Time Systems
Oct 2010
Multi-core processors are anticipated to become a major development platform for real-time systems. However, existing power management algorithms are not designed to sufficiently utilize the...
Provided by University of Tennessee
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White Papers
Dynamic Power Partitioning and Control for Performance Optimization in Chip Multiprocessors
Nov 2009
Since power consumption has become a major constraint for the further throughput improvement of Chip MultiProcessors (CMPs), a key challenge is to optimize the performance of a CMP within a power...
Provided by University of Tennessee
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White Papers
PAUC: Power-Aware Utilization Control in Distributed Real-Time Systems
Aug 2010
CPU utilization control has recently been demonstrated to be an effective way of meeting end-to-end deadlines for distributed real-time systems running in unpredictable environments. However,...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Achieving Bounded Matching Delay and Maximized Throughput in Information Dissemination Management
Jan 2011
The demand for high performance information dissemination is increasing in many applications, such as ecommerce and security alerting systems. These applications usually require that the desired...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
DEUCON: Decentralized End-to-End Utilization Control for Distributed Real-Time Systems
Jul 2007
Many real-time systems must control their CPU utilizations in order to meet end-to-end deadlines and prevent overload. Utilization control is particularly challenging in distributed real-time...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Adaptive Power Control With Online Model Estimation for Chip Multiprocessors
Oct 2010
As Chip Multiprocessors (CMPs) become the main trend in processor development, various power and thermal management strategies have recently been proposed to optimize system performance while...
Provided by University of Tennessee
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White Papers
A Low-Power Globally Synchronous Locally Asynchronous FFT Processor
Sep 2007
Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to efficient in order to achieve...
Provided by Springer Science+Business Media
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White Papers
Performance Evaluation of View-Oriented Parallel Programming on Cluster of Computers
Sep 2007
View-Oriented Parallel Programming(VOPP) is a novel programming style based on Distributed Shared Memory, which is friendly and easy for programmers to use. In this paper the authors compare VOPP...
Provided by Springer Science+Business Media
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White Papers
Parallel Genetic Algorithms for DVS Scheduling of Distributed Embedded Systems
Sep 2007
Many of today's embedded systems, such as wireless and portable devices rely heavily on the limited power supply. Therefore, energy efficiency becomes one of the major design concerns for embedded...
Provided by Springer Science+Business Media
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White Papers
A Holistic Approach for Performance Measurement and Analysis for Petascale Applications
Mar 2009
Contemporary high-end Terascale and Petascale systems are composed of hundreds of thousands of commodity multi-core processors interconnected with high-speed custom networks. Performance...
Provided by University of Oregon
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White Papers
Grouping-Based Dynamic Power Management for Multi-Threaded Programs in Chip-Multiprocessors
May 2009
In the embedded systems field, the research focus has shifted from performance to considering both performance and power consumption. Previous research has investigated methods to forecast the...
Provided by Institute of Electrical and Electronics Engineers
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