Development and Evaluation of a Memory Consistency and Cache Coherence Protocol for the Nocsim NoC Simulator
Source: KTH - Royal Institute of Technology
Networks on Chip (NoC) have started to replace conventional buses, especially in systems on chip and distributed systems. In a typical system with a bus, cache coherency and memory consistency problems are handled by commonly known protocols. Some features of these solutions for bus based systems can be applied to network on chip as well. However, there usually are some complications when those solutions are implemented on a network on chip. This paper offers a solution to the cache coherency and memory consistency problems with implemented proposals which are designed to work on Nocsim Nostrum simulator using the ForSyDe library which was developed at KTH.
| Format: | Size: | 746.90 | |
| Date: | Feb 2008 |



