Efficient Fault Tolerant Adaptive Routing for Spidergon NoC Architecture
The wide range of on chip network applications' performance demands adopting different architectures suited for an application. The performance of a topology can be improved by employing different methods and techniques. In this paper, an efficient Dynamic Stress Wormhole Routing (DWSR) algorithm has been presented for the Spidergon architecture of Networks on Chip (NoC). The adaptive routing always considers the shortest path to route the packets incase of faulty nodes or links. Apart from rerouting the packets, it also distributes the load across the network. The results show that the DSWR algorithm performs better than the deterministic algorithm.