Embedding High-Performance Synchronous Routers to Asynchronous Network on Chip

The speculation and flit-reservation techniques have been used maturely in high-performance synchronous routers. Those high-performance router designs are based on snapshot points capturing the state of the routers at each clock cycle. However, in asynchronous circuits, it is impossible to capture the snapshot information due to their asynchronous and non-deterministic behavior. In this paper, the authors propose a new design scheme for embedding those high-performance synchronous routers onto an asynchronous Network on Chip (NoC) to achieve advantages of both synchronous and asynchronous designs. They analyze the latency-performance of the proposed scheme with previously available schemes. Finally, the advantages of the deterministic behavior in the proposed embedding method are discussed at the viewpoint of 'Quality of service' and 'Testability'.