Evaluating Voltage Islands in CMPs under Process Variations

Parameter variations are a major factor causing power-performance asymmetry in chip multiprocessors. In this paper, the authors analyze the effects of With-In-Die (WID) process variations on chip multicore processors and then apply a variable voltage island scheme to minimize power dissipation. Their idea is based on the observation that due to process variations, the critical paths in each core are likely to have a different latencies resulting in Core-To-Core (C2C) variations. As a result, each core can operate correctly under different supply voltage levels, achieving an optimal power consumption level. Particularly, they analyze voltage islands at different granularities ranging from a single core to a group of cores.