Exploiting Narrow Accelerators With Data-Centric Subgraph Mapping

The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a software perspective, are difficult or impossible to integrate in many modern architectures, though, due to area and timing requirements. This reality is coupled with the observation that many application domains under-utilize accelerator hardware, because of the narrow data they operate on and the nature of their computation. In this paper, the authors take advantage of these facts to design accelerators capable of executing in modern architectures by narrowing datapath width and reducing interconnect.