Flexible Hardware-Based Stereo Matching

To enable adaptive stereo vision for hardware-based embedded stereo vision systems, the authors propose a novel technique for implementing a flexible block size, disparity range, and frame rate. By reusing existing resources of a static architecture, rather than dynamic reconfiguration, their technique is compatible with Application Specific Integrated Circuit (ASIC) as well as Field Programmable Gate Array (FPGA) implementations. They present the corresponding block diagrams and their implementation in their hardware-based stereo matching architecture. Furthermore, they show the impact of flexible stereo matching on the generated disparity maps for the Sum of Absolute Differences (SADs), rank, and census transform algorithms. Finally, they discuss the resource usage and achievable performance when synthesized for an Altera Stratix II FPGA.