FPGA Implementation of DES Using Pipelining Concept With Skew Core Key-Scheduling
This paper presents a high-performance reconfigurable hardware implementation of the Data Encryption Standard (DES) algorithm. This is achieved by combining pipelining concept with novel skew core key scheduling method and compared with previous illustrated encryption algorithms. The DES design is implemented on Xilinx Spartan-3e Field Programming Gate Arrays (FPGA) technology. Final 16-stage pipelined design is achieved with encryption rate of 7.160 Gbit/s and 2814 number of Configurable Logic Blocks (CLBs). This result is among the fastest hardware implementations with better area utilization.