Functional Correctness for CMP Interconnects
Source: University of Michigan
As transistor counts continue to scale, modern designs are transitioning towards large Chip Multi-Processors (CMPs). In order to match the advancing performance of CMPs, on-chip interconnects are becoming increasingly complex, commonly deploying advanced Network-on-Chip (NoC) structures. Ensuring the correct operation of these system-level infrastructures has become increasingly problematic and, in order to avoid the potential for functional design errors manifesting into the final product, there is a need for mechanisms to safeguard communication integrity at runtime. In this paper, the authors propose SafeNoC, an end-to-end error detection and recovery solution to ensure the functional correctness of CMP interconnects.