Hardware Architecture for Simultaneous Arithmetic Coding and Encryption

Arithmetic coding is increasingly being used in upcoming image and video compression standards such as JPEG2000, and MPEG-4/H.264 AVC and SVC standards. It provides an efficient way of loss-less compression and recently, it has been used for joint compression and encryption of video data. In this paper, the authors present an interpretation of arithmetic coding using chaotic maps. This interpretation greatly reduces the hardware complexity of decoder to use a single multiplier by using an alternative algorithm and enables encryption of video data at negligible computational cost.