High Speed 1-Bit Bypass Adder Design for Low Precision Additions

In this paper, the authors propose a high speed adder which is adopted for the reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture adopts 8-bit processing units as the atomic operation. Hence, high speed 8-bit adders are a key building block necessary for high performance. The proposed adder intends to speed up 8-bit adder operations. It is based on a conventional bypass adder scheme, but bypasses 2 bits on every adder bit stage rather than bypassing 4 bits on every four bit stages for conventional bypass adders. The proposed adder enables high speed operation for the FleXilicon and maximizes sub-word parallelism.