Integrated Code and Data Placement in Two-Dimensional Mesh Based Chip Multiprocessors

As transistor sizes continue to shrink and the number of transistors per chip keeps increasing, Chip MultiProcessors (CMPs) are becoming a promising alternative to remain on the current performance trajectory for both high-end systems and embedded systems. Since future technologies offer the promise of being able to integrate billions of transistors on a chip, the prospects of having hundreds to thousands of processors on a single chip along with an underlying memory hierarchy and an interconnection system is entirely feasible. This paper proposes a compiler directed integrated code and data placement scheme for two dimensional mesh based CMP architectures.