Limits and Opportunities for Designing Manycore Processor-to-Memory Networks Using Monolithic Silicon Photonics

To sustain the historic performance improvement in VLSI systems, while remaining within the power envelope, the trend has moved towards designing multiple cores on a single die. However, if designed using current and/or projected electrical solutions, these systems would quickly get bandwidth-limited due to bandwith density limitations and power constraints. It is therefore necessary to explore alternate interconnect technologies like silicon photonics that could provide high bandwidth density and energy-efficient data transmission. Here, the authors summarize the results from their study to determine the limits and opportunities for using silicon photonic technology for designing core-to-memory i.e. off-chip interconnect networks in manycore systems.