Logic Soft Errors in a Parallel CISC Decoder
The instruction decoder is one of the most complex and least regular logic structures in a modern processor that attempts to process multiple variable-length CISC instructions per cycle. This structure consumes a significant amount of area and is heavily utilized, making it vulnerable to logic soft errors. This paper analyzes a parallel decoder using gate-level modeling and statistical fault injection, and finds that the conventional Single-Event Upset (SEU) approach is inadequate for modeling the effects of soft errors in this circuit. The authors also show that different sections of the decoder design have very different fault propagation characteristics, and discuss the suitability of various approaches for protecting such circuits.