Low Power Gated Bus Synthesis Using Shortest-Path Steiner Graph for System-on-Chip Communications
Power consumption of system-level on-chip communications is becoming more significant in the overall System-On-Chip (SoC) power as technology scales down. In this paper, the authors propose a low power design technique of gated bus which can greatly reduce power consumption on state-of-the-art bus architectures. By adding demultiplxers and adopting a novel shortest-path Steiner graph, they achieve a flexible tradeoff between large power reduction versus small wire-length increment. According to the experiments, using the gated bus they can reduce on average 93.2% of wire capacitance per transaction, nearly half of bus dynamic power and on a scale of 5%~10% of total system power.