Low Power Implementation of Triple-Des Block 65nm Technology
Power and delay are two main constraints in ASCI design. Trying to optimize the design with respect to power might result in an increase in the delay. This trade-off between power and delay are analyzed in this paper. In this design both mixed vt and clock gating techniques (mixed design) are used to reduce power. The TDES block is Place and Routed using Soc Encounter by using the above mentioned mixed design methodology. Therefore by analyzing the power delay tradeoff the authors suggest the best technique for TRIDES MAC block is the mixed design method.