Mapping Optimisation for Scalable Multi-Core ARchiTecture: The MOSART Approach
Source: Institute of Electrical and Electronics Engineers
The project will address two main challenges of prevailing architectures: The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; the difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications.
| Format: | Size: | 1665.30 | |
| Date: | Apr 2010 |



