Memory Footprint Reduction for FPGA Routing Algorithms

In this paper, the authors present a technique to reduce the run-time memory footprint of FPGA routing algorithms. These algorithms require a representation of the physical routing resources and programmable connections on the device; this representation dominates the storage requirements of FPGA routers. They show that by taking advantage of the tile-based nature of FPGAs, they can reduce the amount of information that must be explicitly represented, leading to significant memory savings. To make their proposal concrete, they applied it to the routing algorithm in VPR and quantified the impact on run-time memory footprint, and place and route compile-time.