Method to Minimize the Clock Skew and Uniform Clock Distribution Using Parallel Port in Pipe Line Based Multi Channel DMA Request Terminal for Frequency Measurement
This paper presents a new wide-range digital speed measurement method with jitter removal technique and using the Direct Memory Access (DMA) Terminal Count Register (TCR). The authors' work also supports a multi node interfacing from different measure ends. The multiple measure ends are interfaced with DMA channels through pipelines to improve hit ratio. Here, hit ratio indicates the exact identification of encoder pulses without any fail or miss. But, the conventional pipeline system is facing problems due to improper synchronization of clock pulses. This is a universal problem in all the digital systems mostly called jitter or skew.