Micro-Pages: Increasing DRAM Efficiency With Locality-Aware Data Placement
Power consumption and DRAM latencies are serious concerns in modern Chip-MultiProcessor (CMP or Multi-core) based compute systems. The management of the DRAM row buffer can significantly impact both power consumption and latency. Modern DRAM systems read data from cell arrays and populate a row buffer as large as 8 KB on a memory request. But only a small fraction of these bits are ever returned back to the CPU. This ends up wasting energy and time to read (And subsequently write back) bits which are used rarely.