MISD Compiler for Feature Vector Computation in Serial Input Images

In this paper a compiler capable of generate Multiple Instruction Single Data (MISD) architectures for feature vector calculation is presented. The input is a high-level language, avoiding to developers to involve in low level design. Instead, the output is expressed in a Hardware Description Language (HDL), and can be used for FPGA configuration. A FPGA is a programmable device which allows parallelism, increasing the system speed up. The tool is intended to use in feature vector calculation of Region Of Interest (ROI) for real time video applications.