Multi-Threading Performance on Commodity Multi-Core Processors

Multi-core processors based commodity servers recently become building blocks for high performance computing Linux clusters. The multi-core processors deliver better performance-to-cost ratios relative to their single-core predecessors through on-chip multi-threading. However, they present challenges in developing high performance multi-threaded code. This paper studies the performance of different software barrier algorithms on Intel Xeon and AMD Opteron multi-core processor based servers. Especially, this paper explores how different memory subsystems, such as shared bus or ccNUMA, and their cache coherence protocols effect the performance of barrier algorithms.