On-Chip Photonic Communication for High-Performance Multi-Core Processors
Source: Columbia University
The quest for high-performance and low-power has brought computer architects to design multi-core architectures where an increasing number of parallel processing cores are integrated on a single die to operate in a tightly coupled fashion. With nanometer technologies, a Chip Multi-Processor (CMP) based on a multi-core architecture delivers better performance-per-watt than a traditional deeply-pipelined superscalar microprocessor running at the highest possible clock frequency. However, in order to fully exploit the processing capabilities offered by the integration of an increasing number of cores, three major challenges must be addressed: the increasing on-chip power dissipation, the limited I/O bandwidth, and the complexity of parallel programming.