On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals

In this paper, the authors present a design methodology for the identification and development of a suitable hardware platform (including dedicated hardware accelerators) for the data plane processing of the LTE protocol stack Layer 2 (L2) in downlink direction. For this purpose, a hybrid design approach is adopted allowing first investigations of future mobile phone platforms on the system level (using virtual prototyping) combined with more accurate power-area explorations of hardware accelerators on the architectural level. Additionally, they show the employment of an LTE data generator peripheral, realizing L2 uplink processing and thus enabling platform analyses in a closed virtual environment. Furthermore, a modeling technique for a fast and efficient design of virtual hardware accelerator peripherals is demonstrated.