Output Process of Variable Bit-Rate Flows in On-Chip Networks Based on Aggregate Scheduling

This paper proposes an approach for more accurate analyzing of output flows in FIFO multiplexing on-chip networks with aggregate scheduling by considering peak behavior of flows. The key idea of the authors' proposed method involves presenting and proving a technical proposition to derive output arrival curve for an individual flow under the mentioned system model. Since the number of real-time communication services being deployed on NoCs is increasing, it is clear that architectures based on aggregate scheduling, which schedule multiple flows as an aggregate flow, will be an appropriate option for transmitting real-time traffic.