Parallelized Progressive Network Coding With Hardware Acceleration

The fundamental insight of network coding is that information to be transmitted from the source in a session can be inferred, or decoded, by the intended receivers, and does not have to be transmitted verbatim. It is a well known result that network coding may achieve better network throughput in certain multicast topologies; however, the practicality of network coding has been questioned, due to its high computational complexity. This paper represents the first attempt towards a high performance implementation of network coding. The authors first propose to implement progressive decoding with Gauss-Jordan elimination, such that blocks can be decoded as they are received. They then employ hardware acceleration with SSE2 and AltiVec SIMD vector instructions on x86 and PowerPC processors, respectively.