Performance Analysis of CORDIC Architectures Targeted for FPGA Devices

Digital Signal Processing domain has long been dominated by software systems; however, the state of art signal processing is now again switching back to hardware based solutions. This requires development of algorithms that can be efficiently implemented on different hardware platforms. CORDIC is one such hardware-efficient algorithm that is used in DSP systems for calculating trigonometric, hyperbolic, logarithmic and other transcendental functions. This paper attempts to explore the different implementations of CORDIC architectures, specific to FPGA devices. The algorithm is implemented in two different styles: folded and unfolded. Unfolded design is improved architecturally by pipelining it.