Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors

The design and performance of next-generation Chip MultiProcessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. The authors present photonic Networks-on-Chip (NoC) as a solution to reduce the impact of intrachip and off-chip communication on the overall power budget. The low loss properties of optical waveguides, combined with bit-rate transparency, allow for a photonic interconnection network that can deliver considerably higher bandwidth and lower latencies with significantly lower power dissipation than an interconnection network based only on electronic signaling. They explain why on-chip photonic communication has recently become a feasible opportunity and explore the challenges that need to be addressed to realize its implementation.