Power Reduction Techniques for LDPC Decoders

This paper investigates hardware architectures for Low-Density Parity-Check (LDPC) decoders amenable to low-voltage and low-power operation. First, highly-parallel decoder architecture with low routing overhead is described. Second, the authors propose an efficient method to detect early convergence of the iterative decoder and terminate the computations, thereby reducing dynamic power. LDPC codes have been adopted for several new digital communication standards due to their excellent error correction performance, freedom from patent protection, and inherently-parallel decoding algorithm. Most of the research on LDPC decoder design so far has focused on code designs, decoding algorithms, and decoder architectures that improve decoder throughput.