PPNOCS: Performance and Power Network on Chip Simulator Based on SystemC
As technology moves towards multi-core System-On-Chips (SoCs), Networks-on-Chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. Network-on-Chip architectures have a wide variety of parameters that can be adapted to the designer's requirements. This paper proposes a Performance and Power Network On Chip simulator (PPNOCS) based on SystemC to explore the impact of various architectural level parameters of the on-chip interconnection network elements on its performance and power. PPNOCS supports an arbitrary size of mesh and torus topology, adopts five classic routing algorithms and seven synthetic traffic patterns. Developers also can develop and verify their own network design by modifying the corresponding modules.