Regular Expression Software Deceleration for Intrusion Detection Systems

The use of reconfigurable hardware for network security applications has recently made great strides as FPGA devices have provided larger and faster resources. Regular expressions have become a necessary and basic capability of Intrusion Detection Systems, but their implementation tends to be expensive in terms of memory cost and time performance. This work provides an architecture that reduces the exponential NFA to DFA conversion cost to a linear growth for many expressions. The use of reconfigurable hardware for network security applications has recently made great strides as FPGA devices have provided larger and faster resources.