Reliable Architecture for Flash Memory
The mounting demand for high density non-volatile flash memories consequences new challenges of flash memory reliability issues [1, 2]. Common reliability-improving techniques approaches are addressing device and process manufacturing improvements  or Error Correction Codes (ECC) techniques . This paper proposes a novel memory architecture and method of increasing reliability through reducing the Program-Erase (P/E) cycles. Reduction of P/E cycles is achieved through a memory architecture which enables rewrite operation in a single flash memory cell, instead erase-and-program which is currently applied. Furthermore, a potential improvement of the write operation time is also achieved when using sufficiently large write buffer, regarding modern write techniques [5, 6].