Run-Time Data-Dependent Defect Tolerance for Hybrid CMOS/Nanodevice Digital Memories

This paper presents a data-dependent defect tolerance design approach to improve the storage capacity of defectprone hybrid CMOS/nanodevice digital memories. The basic idea is to reduce the memory redundancy overhead by exploiting the run-time matching between the data to be stored and the memory defects. A conditional bit-flipping technique is used to enable the practical realization of this design approach in presence of the conflict between the dynamic nature of run-time datadefect matching and static nature of memory system design. Computer simulation results demonstrate that the proposed method can achieve much higher storage capacity compared with conventional data-independent defect tolerance at small memory operation overhead.