- Subscribe to this page:
- RSS
- Email Alert
risc-based servers
(28 results)-
White Papers
Intel Multi-Core Processors: Making the Move to Quad-Core and Beyond
Sep 2006
This paper explains the advantages and challenges of multi-core processing, plus provides a glimpse into the upcoming Intel quad-core processors and the direction in which Intel is taking...
Provided by Intel
-
Case Studies
Batch Processing Tasks Are 40 Percent Faster With Dell PowerEdge Servers
May 2009
DataVision was seeking an alternative hardware solution to recommend to its banking clients, which would offer high performance and support in remote areas without requiring a compromise on cost....
Provided by Intel
-
White Papers
Staff Cost Savings Models to Justify RISC Migration
Apr 2009
In the past, RISC-based servers delivered performance and memory advantages that made them the workhorses of corporate computing. And even though the systems used expensive, proprietary components...
Provided by Ziff Davis Enterprise Holdings
-
White Papers
Migrating From UNIX/RISC to Red Hat Enterprise Linux on Intel Processor-Based Servers: Driving Higher Value Deep Into the Data Center
Jul 2009
Red Hat Enterprise Linux running on Intel processor-based servers is helping companies cut TCO by up to 50 percent and more versus comparable UNIX/RISC solutions, while providing a better...
Provided by Intel
-
Whitepapers
Failover of Oracle Database Between HP 9000 (PA-RISC) Servers and HP Integrity (IPF) Servers Under HP-UX 11i
Jul 2009
HP's Intel Itanium-based Integrity architecture was designed to employ the same data format as PA-RISC-based HP 9000 architecture, which gives rise to all manner of cross-architectural scenarios...
Provided by Hewlett-Packard (HP)
-
White Papers
Migrating Infrastructure for SAP Environments Away From Unix/RISC
Aug 2009
In this white paper, the authors will look into three distinct customer situations faced with the business driver to move from an Unix/RISC system supporting an SAP ERP system each to another...
Provided by IDG (International Data Group)
-
Case Studies
Farmalink Readies for Continued Growth With Hp Integrity Server Blades
Oct 2008
Farmalink is dedicated to administering and auditing prescription drug plans for health insurance agents. Farmalink wanted to establish a flexible, adaptable infrastructure that can continue...
Provided by Hewlett-Packard (HP)
-
Webcasts
Virtualization Business Benefits
Jan 2010
Intel and VMware discuss the business benefits of virtualization including the increased utilization of hardware resources by having more virtual machines per single server. Reducing hardware...
Provided by Intel
-
White Papers
TELUS Communications
Oct 2010
One of Canada's leading national telecommunications companies, TELUS delivers data, IP, voice, entertainment and video services to over 12 million consumer connections, and offers business...
Provided by VMware
-
White Papers
Power-Efficient Instruction Encoding Optimization for Various Architecture Classes
Mar 2008
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with Application...
Provided by Academy Publisher
-
White Papers
SARA: Combining Stack Allocation and Register Allocation
Jan 2011
Commonly-used memory units enable a processor to load and store multiple registers in one instruction. The authors showed in 2003 how to extend gcc with a Stack-Location-Allocation (SLA) phase...
Provided by University of California
-
White Papers
SSA Elimination After Register Allocation
Jan 2009
Compilers such as gcc use Static-Single-Assignment (SSA) form as an intermediate representation and usually perform SSA elimination before register allocation. But the order could as well be the...
Provided by University of California
-
Whitepapers
HP-UX 11i V3: Engineered for Critical Workloads
Aug 2010
In recent years, UNIX systems have matured sufficiently to meet the functional requirements of the most demanding environments in the industry. HP was one of the first major vendors to envision...
Provided by Hewlett-Packard (HP)
-
White Papers
Temporal Instruction Fetch Streaming
Sep 2008
L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough to capture the...
Provided by Carnegie Mellon University
-
White Papers
RDF3X: A RISC-Style Engine for RDF
Aug 2008
RDF is a data representation format for schema-free structured information that is gaining momentum in the context of Semantic-Web corpora, life sciences, and also Web 2.0 platforms. The...
Provided by VLDB Endowment
-
Whitepapers
Processor Realization for Application of Convolution
Aug 2012
Convolution is very important in signal and image processing applications which is used in filter designing. Many algorithms have been proposed in order to accomplish an improved the performance...
Provided by International Journal of Engineering Research and Development (IJERD)
-
Whitepapers
FPGA Based Implementation of 32 Bit RISC Processor
Jul 2011
In this paper, a design of general purpose processor with a 5 stage pipeline, to incorporate programmable resources in to a processor. RISC processors have a CPI (clock per instruction) of one...
Provided by International Journal of Engineering Research and Applications (IJERA)
-
Whitepapers
Realization of Dualcore IBM Power5 Fine Grained Multithreaded Processor
Aug 2012
In the present world the computer has become an essential and inevitable part in any field and industry be it in administrative field, science, defense or in any other field. The processor...
Provided by International Journal of Electronics and Computer Science Engineering
-
Whitepapers
Study of 32-bit RISC Processor Architecture and VHDL FPGA Implementation 32-bit Matrix Manipulation
Oct 2011
Present paper discloses a distinctive method to cram the processor behavior while dealing with the multifaceted task of matrix manipulation. System facilitates this distinct feature by allowing...
Provided by International Journal of Computer Applications
-
Whitepapers
IBM Power Systems - Cost-effective Linux database serving
May 2008
Maintaining data security, performance, availability and recoverability is a growing challenge. The IBM Power platform offers cost-effective performance, scalability and key functional...
Provided by IBM
-
Whitepapers
A Super Scalar Sort Algorithm for RISC Processors
Nov 2007
The compare and branch sequences required in a traditional sort algorithm can not efficiently exploit multiple execution units present in currently available high performance RISC processors. This...
Provided by IBM
-
White Papers
RISC Processor Based Speech Codec Implementation for Emerging Mobile Multimedia Messaging Solutions
Jan 2008
Mobile Multimedia Messaging (MMS) promises to provide a richer and versatile experience to the user along with new revenue streams for mobile service operators. MMS allows a full content range...
Provided by Aricent
-
Whitepapers
Modeling of ARM Cortex-M3 Processor Core Using SystemC
Dec 2011
RISC architecture is extensively preferred for the development of high end embedded application in increasing demand like mobile phones with space and power constraints. This has led to...
Provided by International Journal on Computer Science and Technology (IJCST)
-
Whitepapers
Processor Architecture Design Practices: Survey & Issues
Jun 2010
The paper explores the recent architecture evaluations and related issues and compares NISC (No Instruction Set Computer) features to those of CISC (Complex Instruction Set Computer) and RISC...
Provided by International Journal of Engineering Science and Technology (IJEST)
-
Whitepapers
FPGA Implementation of a MIPS RISC Processor
Jun 2012
This paper targets the implementation design of a MIPS (Microprocessor without Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor using VHDL (Very high speed integrated...
Provided by International Journal of Computer Technology and Applications
-
Whitepapers
Designing and Optimizing the Fetch Unit for a RISC Core
Sep 2010
Despite the extensive deployment of multi-core architectures in the past few years, the design and optimization of each single processing core is still a fresh field in computing. On the other...
Provided by Amirkabir University of Technology
-
Whitepapers
CHERI: A Research Platform Deconflating Hardware Virtualization and Protection
Feb 2012
Contemporary CPU architectures conflate virtualization and protection, imposing virtualization-related performance, programmability, and debuggability penalties on software requiring fine-grained...
Provided by University of Cambridge
-
White Papers
When Good Instructions Go Bad: Generalizing Return-Oriented Programming to RISC
Oct 2008
This paper reconsiders the threat posed by Shacham's "Return-oriented programming" - a technique by which OX-style hardware protections are evaded via carefully crafted stack frames that divert...
Provided by Association for Computing Machinery
-
Whitepapers
Study of 32-bit RISC Processor Architecture and VHDL FPGA Implementation 32-bit Matrix Manipulation
Oct 2011
Present paper discloses a distinctive method to cram the processor behavior while dealing with the multifaceted task of matrix manipulation. System facilitates this distinct feature by allowing...
Provided by International Journal of Computer Applications
-
Whitepapers
Realization of Dualcore IBM Power5 Fine Grained Multithreaded Processor
Aug 2012
In the present world the computer has become an essential and inevitable part in any field and industry be it in administrative field, science, defense or in any other field. The processor...
Provided by International Journal of Electronics and Computer Science Engineering
-
Whitepapers
FPGA Based Implementation of 32 Bit RISC Processor
Jul 2011
In this paper, a design of general purpose processor with a 5 stage pipeline, to incorporate programmable resources in to a processor. RISC processors have a CPI (clock per instruction) of one...
Provided by International Journal of Engineering Research and Applications (IJERA)
-
Whitepapers
Processor Realization for Application of Convolution
Aug 2012
Convolution is very important in signal and image processing applications which is used in filter designing. Many algorithms have been proposed in order to accomplish an improved the performance...
Provided by International Journal of Engineering Research and Development (IJERD)
-
Whitepapers
CHERI: A Research Platform Deconflating Hardware Virtualization and Protection
Feb 2012
Contemporary CPU architectures conflate virtualization and protection, imposing virtualization-related performance, programmability, and debuggability penalties on software requiring fine-grained...
Provided by University of Cambridge
-
Whitepapers
Designing and Optimizing the Fetch Unit for a RISC Core
Sep 2010
Despite the extensive deployment of multi-core architectures in the past few years, the design and optimization of each single processing core is still a fresh field in computing. On the other...
Provided by Amirkabir University of Technology
-
Whitepapers
FPGA Implementation of a MIPS RISC Processor
Jun 2012
This paper targets the implementation design of a MIPS (Microprocessor without Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor using VHDL (Very high speed integrated...
Provided by International Journal of Computer Technology and Applications
-
Whitepapers
Processor Architecture Design Practices: Survey & Issues
Jun 2010
The paper explores the recent architecture evaluations and related issues and compares NISC (No Instruction Set Computer) features to those of CISC (Complex Instruction Set Computer) and RISC...
Provided by International Journal of Engineering Science and Technology (IJEST)
-
Whitepapers
Modeling of ARM Cortex-M3 Processor Core Using SystemC
Dec 2011
RISC architecture is extensively preferred for the development of high end embedded application in increasing demand like mobile phones with space and power constraints. This has led to...
Provided by International Journal on Computer Science and Technology (IJCST)
-
White Papers
RDF3X: A RISC-Style Engine for RDF
Aug 2008
RDF is a data representation format for schema-free structured information that is gaining momentum in the context of Semantic-Web corpora, life sciences, and also Web 2.0 platforms. The...
Provided by VLDB Endowment
-
White Papers
Temporal Instruction Fetch Streaming
Sep 2008
L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough to capture the...
Provided by Carnegie Mellon University
-
Whitepapers
HP-UX 11i V3: Engineered for Critical Workloads
Aug 2010
In recent years, UNIX systems have matured sufficiently to meet the functional requirements of the most demanding environments in the industry. HP was one of the first major vendors to envision...
Provided by Hewlett-Packard (HP)
-
White Papers
SSA Elimination After Register Allocation
Jan 2009
Compilers such as gcc use Static-Single-Assignment (SSA) form as an intermediate representation and usually perform SSA elimination before register allocation. But the order could as well be the...
Provided by University of California
-
White Papers
SARA: Combining Stack Allocation and Register Allocation
Jan 2011
Commonly-used memory units enable a processor to load and store multiple registers in one instruction. The authors showed in 2003 how to extend gcc with a Stack-Location-Allocation (SLA) phase...
Provided by University of California
-
White Papers
Power-Efficient Instruction Encoding Optimization for Various Architecture Classes
Mar 2008
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with Application...
Provided by Academy Publisher
-
White Papers
TELUS Communications
Oct 2010
One of Canada's leading national telecommunications companies, TELUS delivers data, IP, voice, entertainment and video services to over 12 million consumer connections, and offers business...
Provided by VMware
-
Webcasts
Virtualization Business Benefits
Jan 2010
Intel and VMware discuss the business benefits of virtualization including the increased utilization of hardware resources by having more virtual machines per single server. Reducing hardware...
Provided by Intel
-
Case Studies
Farmalink Readies for Continued Growth With Hp Integrity Server Blades
Oct 2008
Farmalink is dedicated to administering and auditing prescription drug plans for health insurance agents. Farmalink wanted to establish a flexible, adaptable infrastructure that can continue...
Provided by Hewlett-Packard (HP)
-
White Papers
Migrating Infrastructure for SAP Environments Away From Unix/RISC
Aug 2009
In this white paper, the authors will look into three distinct customer situations faced with the business driver to move from an Unix/RISC system supporting an SAP ERP system each to another...
Provided by IDG (International Data Group)
-
Whitepapers
Failover of Oracle Database Between HP 9000 (PA-RISC) Servers and HP Integrity (IPF) Servers Under HP-UX 11i
Jul 2009
HP's Intel Itanium-based Integrity architecture was designed to employ the same data format as PA-RISC-based HP 9000 architecture, which gives rise to all manner of cross-architectural scenarios...
Provided by Hewlett-Packard (HP)
-
White Papers
Migrating From UNIX/RISC to Red Hat Enterprise Linux on Intel Processor-Based Servers: Driving Higher Value Deep Into the Data Center
Jul 2009
Red Hat Enterprise Linux running on Intel processor-based servers is helping companies cut TCO by up to 50 percent and more versus comparable UNIX/RISC solutions, while providing a better...
Provided by Intel
-
White Papers
Staff Cost Savings Models to Justify RISC Migration
Apr 2009
In the past, RISC-based servers delivered performance and memory advantages that made them the workhorses of corporate computing. And even though the systems used expensive, proprietary components...
Provided by Ziff Davis Enterprise Holdings
-
Case Studies
Batch Processing Tasks Are 40 Percent Faster With Dell PowerEdge Servers
May 2009
DataVision was seeking an alternative hardware solution to recommend to its banking clients, which would offer high performance and support in remote areas without requiring a compromise on cost....
Provided by Intel
-
White Papers
When Good Instructions Go Bad: Generalizing Return-Oriented Programming to RISC
Oct 2008
This paper reconsiders the threat posed by Shacham's "Return-oriented programming" - a technique by which OX-style hardware protections are evaded via carefully crafted stack frames that divert...
Provided by Association for Computing Machinery
-
White Papers
RISC Processor Based Speech Codec Implementation for Emerging Mobile Multimedia Messaging Solutions
Jan 2008
Mobile Multimedia Messaging (MMS) promises to provide a richer and versatile experience to the user along with new revenue streams for mobile service operators. MMS allows a full content range...
Provided by Aricent
-
Whitepapers
A Super Scalar Sort Algorithm for RISC Processors
Nov 2007
The compare and branch sequences required in a traditional sort algorithm can not efficiently exploit multiple execution units present in currently available high performance RISC processors. This...
Provided by IBM
-
Whitepapers
IBM Power Systems - Cost-effective Linux database serving
May 2008
Maintaining data security, performance, availability and recoverability is a growing challenge. The IBM Power platform offers cost-effective performance, scalability and key functional...
Provided by IBM
-
White Papers
Intel Multi-Core Processors: Making the Move to Quad-Core and Beyond
Sep 2006
This paper explains the advantages and challenges of multi-core processing, plus provides a glimpse into the upcoming Intel quad-core processors and the direction in which Intel is taking...
Provided by Intel
-
Case Studies
Batch Processing Tasks Are 40 Percent Faster With Dell PowerEdge Servers
May 2009
DataVision was seeking an alternative hardware solution to recommend to its banking clients, which would offer high performance and support in remote areas without requiring a compromise on cost....
Provided by Intel
-
White Papers
Staff Cost Savings Models to Justify RISC Migration
Apr 2009
In the past, RISC-based servers delivered performance and memory advantages that made them the workhorses of corporate computing. And even though the systems used expensive, proprietary components...
Provided by Ziff Davis Enterprise Holdings
-
White Papers
Migrating From UNIX/RISC to Red Hat Enterprise Linux on Intel Processor-Based Servers: Driving Higher Value Deep Into the Data Center
Jul 2009
Red Hat Enterprise Linux running on Intel processor-based servers is helping companies cut TCO by up to 50 percent and more versus comparable UNIX/RISC solutions, while providing a better...
Provided by Intel
-
Whitepapers
Failover of Oracle Database Between HP 9000 (PA-RISC) Servers and HP Integrity (IPF) Servers Under HP-UX 11i
Jul 2009
HP's Intel Itanium-based Integrity architecture was designed to employ the same data format as PA-RISC-based HP 9000 architecture, which gives rise to all manner of cross-architectural scenarios...
Provided by Hewlett-Packard (HP)
-
White Papers
Migrating Infrastructure for SAP Environments Away From Unix/RISC
Aug 2009
In this white paper, the authors will look into three distinct customer situations faced with the business driver to move from an Unix/RISC system supporting an SAP ERP system each to another...
Provided by IDG (International Data Group)
-
Case Studies
Farmalink Readies for Continued Growth With Hp Integrity Server Blades
Oct 2008
Farmalink is dedicated to administering and auditing prescription drug plans for health insurance agents. Farmalink wanted to establish a flexible, adaptable infrastructure that can continue...
Provided by Hewlett-Packard (HP)
-
Webcasts
Virtualization Business Benefits
Jan 2010
Intel and VMware discuss the business benefits of virtualization including the increased utilization of hardware resources by having more virtual machines per single server. Reducing hardware...
Provided by Intel
-
White Papers
TELUS Communications
Oct 2010
One of Canada's leading national telecommunications companies, TELUS delivers data, IP, voice, entertainment and video services to over 12 million consumer connections, and offers business...
Provided by VMware
-
White Papers
Power-Efficient Instruction Encoding Optimization for Various Architecture Classes
Mar 2008
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with Application...
Provided by Academy Publisher
-
White Papers
Intel Multi-Core Processors: Making the Move to Quad-Core and Beyond
Sep 2006
This paper explains the advantages and challenges of multi-core processing, plus provides a glimpse into the upcoming Intel quad-core processors and the direction in which Intel is taking...
Provided by Intel
-
White Papers
SARA: Combining Stack Allocation and Register Allocation
Jan 2011
Commonly-used memory units enable a processor to load and store multiple registers in one instruction. The authors showed in 2003 how to extend gcc with a Stack-Location-Allocation (SLA) phase...
Provided by University of California
-
White Papers
SSA Elimination After Register Allocation
Jan 2009
Compilers such as gcc use Static-Single-Assignment (SSA) form as an intermediate representation and usually perform SSA elimination before register allocation. But the order could as well be the...
Provided by University of California
-
Whitepapers
HP-UX 11i V3: Engineered for Critical Workloads
Aug 2010
In recent years, UNIX systems have matured sufficiently to meet the functional requirements of the most demanding environments in the industry. HP was one of the first major vendors to envision...
Provided by Hewlett-Packard (HP)
-
White Papers
Temporal Instruction Fetch Streaming
Sep 2008
L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough to capture the...
Provided by Carnegie Mellon University
-
White Papers
RDF3X: A RISC-Style Engine for RDF
Aug 2008
RDF is a data representation format for schema-free structured information that is gaining momentum in the context of Semantic-Web corpora, life sciences, and also Web 2.0 platforms. The...
Provided by VLDB Endowment
-
Whitepapers
Processor Realization for Application of Convolution
Aug 2012
Convolution is very important in signal and image processing applications which is used in filter designing. Many algorithms have been proposed in order to accomplish an improved the performance...
Provided by International Journal of Engineering Research and Development (IJERD)
-
Whitepapers
FPGA Based Implementation of 32 Bit RISC Processor
Jul 2011
In this paper, a design of general purpose processor with a 5 stage pipeline, to incorporate programmable resources in to a processor. RISC processors have a CPI (clock per instruction) of one...
Provided by International Journal of Engineering Research and Applications (IJERA)
-
Whitepapers
Realization of Dualcore IBM Power5 Fine Grained Multithreaded Processor
Aug 2012
In the present world the computer has become an essential and inevitable part in any field and industry be it in administrative field, science, defense or in any other field. The processor...
Provided by International Journal of Electronics and Computer Science Engineering
-
Whitepapers
Study of 32-bit RISC Processor Architecture and VHDL FPGA Implementation 32-bit Matrix Manipulation
Oct 2011
Present paper discloses a distinctive method to cram the processor behavior while dealing with the multifaceted task of matrix manipulation. System facilitates this distinct feature by allowing...
Provided by International Journal of Computer Applications
-
Whitepapers
IBM Power Systems - Cost-effective Linux database serving
May 2008
Maintaining data security, performance, availability and recoverability is a growing challenge. The IBM Power platform offers cost-effective performance, scalability and key functional...
Provided by IBM
-
Whitepapers
A Super Scalar Sort Algorithm for RISC Processors
Nov 2007
The compare and branch sequences required in a traditional sort algorithm can not efficiently exploit multiple execution units present in currently available high performance RISC processors. This...
Provided by IBM
-
White Papers
RISC Processor Based Speech Codec Implementation for Emerging Mobile Multimedia Messaging Solutions
Jan 2008
Mobile Multimedia Messaging (MMS) promises to provide a richer and versatile experience to the user along with new revenue streams for mobile service operators. MMS allows a full content range...
Provided by Aricent
-
Whitepapers
Modeling of ARM Cortex-M3 Processor Core Using SystemC
Dec 2011
RISC architecture is extensively preferred for the development of high end embedded application in increasing demand like mobile phones with space and power constraints. This has led to...
Provided by International Journal on Computer Science and Technology (IJCST)
-
Whitepapers
Processor Architecture Design Practices: Survey & Issues
Jun 2010
The paper explores the recent architecture evaluations and related issues and compares NISC (No Instruction Set Computer) features to those of CISC (Complex Instruction Set Computer) and RISC...
Provided by International Journal of Engineering Science and Technology (IJEST)
-
Whitepapers
FPGA Implementation of a MIPS RISC Processor
Jun 2012
This paper targets the implementation design of a MIPS (Microprocessor without Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor using VHDL (Very high speed integrated...
Provided by International Journal of Computer Technology and Applications
-
Whitepapers
Designing and Optimizing the Fetch Unit for a RISC Core
Sep 2010
Despite the extensive deployment of multi-core architectures in the past few years, the design and optimization of each single processing core is still a fresh field in computing. On the other...
Provided by Amirkabir University of Technology
-
Whitepapers
CHERI: A Research Platform Deconflating Hardware Virtualization and Protection
Feb 2012
Contemporary CPU architectures conflate virtualization and protection, imposing virtualization-related performance, programmability, and debuggability penalties on software requiring fine-grained...
Provided by University of Cambridge
-
White Papers
When Good Instructions Go Bad: Generalizing Return-Oriented Programming to RISC
Oct 2008
This paper reconsiders the threat posed by Shacham's "Return-oriented programming" - a technique by which OX-style hardware protections are evaded via carefully crafted stack frames that divert...
Provided by Association for Computing Machinery
