StageNet: A Reconfigurable CMP Fabric for Resilient Systems
Source: University of Michigan
Though CMOS feature size scaling has been the source of dramatic performance gains, this scaling has lead to mounting reliability concerns due to increasing power densities and on-chip temperatures. Given that most wearout mechanisms that plague semiconductor devices are highly dependent on these parameters, significantly higher failure rates are projected for future technology generations. Traditional techniques for dealing with device failures have relied on the coarse-grained replication of structures (typically at the processor core level) to maintain service in the face of failed components.