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(136 results)-
Webcasts
Webcast: Ubuntu Cloud
Nov 2011
After years of development and fine tuning, the cloud vision of true computing elasticity is finally a reality. The question now is how organizations can best take advantage of the latest cloud...
Provided by Canonical Ltd
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Whitepapers
The Evolution of the Electronics Industry
May 2012
Transistor by transistor, the electronics industry is literally changing the world. Consider the following: today's fastest computers can now achieve 10 quadrillion operations a second1; by 2015,...
Provided by IBM
-
Whitepapers
Top 10 questions about Ubuntu Server Edition
Jul 2011
What's different about Ubuntu Server? Is it secure enough to use in my business? Will it work on my hardware? Whether you've already deployed Ubuntu in your business or are just starting to...
Provided by Canonical Ltd
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Case Studies
Advanced Micro Devices Case Study: Bentley Systems Software
Jan 2009
With over 2,800 colleagues in over 50 offices worldwide and annual revenues surpassing $450 million, Bentley Systems has invested over $I billion in research, development and acquisitions since...
Provided by Advanced Micro Devices (AMD)
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White Papers
Incident Response: Speed Can Mean the Difference Between Success and Failure
Nov 2009
When it comes to investigations and incident response speed is all important. The faster an examiner gets the data in a consumable form the faster an incident can be diagnosed and resolved. Even...
Provided by AccessData
-
White Papers
Redundant Optical Storage System Using DVD-RAM Library
May 2009
A Digital Virtual Disk (DVD) Random Access Memory (RAM) Redundant Array of Inexpensive Libraries (RAIL) optical storage system has been developed and tested at NTT Integrated Information & Energy...
Provided by NTT Communication Science Laboratories
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White Papers
The Value of Using ECC Memory in Embedded Applications
Oct 2009
This paper provides an introduction to Error Correcting Code (ECC) DRAM. It discusses the risks of a system encountering random memory errors and the approaches for combating them. DRAM is...
Provided by Advanced Micro Devices
-
White Papers
Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces
Nov 2007
The DDR3 SDRAM memory architectures support higher bandwidths with bus rates of 600 Mbps to 1.6 Gbps (300 to 800 MHz), 1.5V operation for lower power, and higher densities of 2 Gbits on a 90-nm...
Provided by Altera
-
White Papers
Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance
Dec 2009
The Phase-Change Random Access Memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmability, low-power...
Provided by Association for Computing Machinery
-
Whitepapers
Storage-Class Memory: The Next Storage System Technology
Sep 2008
Maintaining the performance growth rate of the 30-yearold system memory and storage hierarchy, primarily based on DRAM (Dynamic RAM) and disks, has become a major challenge in the design of...
Provided by IBM
-
White Papers
Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores
Jun 2010
DRAM vendors have traditionally optimized the cost-per-bit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, where a single...
Provided by Association for Computing Machinery
-
White Papers
Micro-Pages: Increasing DRAM Efficiency With Locality-Aware Data Placement
Mar 2010
Power consumption and DRAM latencies are serious concerns in modern Chip-MultiProcessor (CMP or Multi-core) based compute systems. The management of the DRAM row buffer can significantly impact...
Provided by Association for Computing Machinery
-
White Papers
Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation With Application to SRAM Circuit Design
Jul 2007
Circuit reliability under statistical process variation is an area of growing concern. For highly replicated circuits such as SRAMs and flip flops, a rare statistical event for one circuit may...
Provided by Carnegie Mellon University
-
White Papers
Extended Abstract: The Butterfly PUF Protecting IP on Every FPGA
Jul 2008
IP protection of hardware designs is the most important requirement for many FPGA IP vendors. To this end, various solutions have been proposed by FPGA manufacturers based on the idea of bitstream...
Provided by Katholieke Universiteit Leuven
-
White Papers
Suitability of Requirements Abstraction Model (RAM) Requirements for High-Level System Testing
Jun 2009
The Requirements Abstraction Model (RAM) helps in managing abstraction in requirements by organizing them at four levels (product, feature, function and component). The RAM is adaptable and can be...
Provided by Katholieke Universiteit Leuven
-
White Papers
3D Network-on-Chip With On-Chip DRAM: An Empirical Analysis for Future Chip Multiprocessor
Nov 2010
With the increasing number of on-chip components and the critical requirement for processing power, Chip MultiProcessor (CMP) has gained wide acceptance in both academia and industry during the...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Low Power SRAM Base on Novel Word-Line Decoding
Jun 2009
This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to...
Provided by Islamic Azad University
-
White Papers
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
Nov 2008
Intermittently-powered applications create a need for low-cost security and privacy in potentially hostile environments, supported by primitives including identification and random number...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Design and Implementation of 8K-Bits Low Power SRAM in 180nm Technology
Mar 2009
This paper explores the tradeoffs that are involved in the design of SRAM. The major components of an SRAM such as the row decoders, the memory cells and the sense amplifiers have been studied in...
Provided by SV College of Engineering & Technology
-
White Papers
Online Memory Compression for Embedded Systems
Feb 2010
Memory is a scarce resource during embedded system design. Increasing memory often increases packaging costs, cooling costs, size, and power consumption. This paper presents CRAMES, a novel and...
Provided by Association for Computing Machinery
-
White Papers
MEMMU: Memory Expansion for MMU-Less Embedded Systems
Apr 2009
Random Access Memory (RAM) is tightly constrained in the least expensive, lowest-power embedded systems such as sensor network nodes and portable consumer electronics. The most widely used sensor...
Provided by Association for Computing Machinery
-
White Papers
Application-Aware NoC Design for Efficient SDRAM Access
Jun 2010
In many-core processors based on Networks-on-Chip (NoC), memory Quality-of-Service (QoS) becomes one of the most important issues since both memory and on-chip network are critical shared...
Provided by Association for Computing Machinery
-
White Papers
An SDRAM-Aware Router for Networks-on-Chip
Jul 2009
This paper presents a NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilization and reduce memory...
Provided by Association for Computing Machinery
-
White Papers
Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup
Jan 2008
Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of today's high-end...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM
Oct 2008
In this paper, the authors present a deep subthreshold 6-T SRAM, which was fabricated in an industrial 0.13 m CMOS technology. The authors first use detailed simulations to explore the challenges...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A 5.42nW/kB Retention Power Logic-Compatible Embedded DRAM With 2T Dual-Vt Gain Cell for Low Power Sensing Applications
Jan 2011
A logic-compatible 2T dual-Vt embedded DRAM (eDRAM) is proposed for ultra-small sensing systems to achieve 8× longer retention time, 5× lower refresh power and 30% reduced area compared with the...
Provided by University of Michigan
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White Papers
SSA - Superblock-Based Storage Architecture: A New Approach for Boosting I/O Performance
Jan 2011
Many of the new I/O architectures like DCD, RAPID cache and LFS focus on improving the disk write performance. However, many I/O intensive applications are read-dominated or generate substantial...
Provided by University of Cincinnati
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White Papers
Joint Coding for Flash Memory Storage
Apr 2008
Flash memory is an electronic non-volatile memory with wide applications. Due to the substantial impact of block erasure operations on the speed, reliability and longevity of flash memories,...
Provided by Texas A&M University
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White Papers
On the Capacity of Bounded Rank Modulation for Flash Memories
Jun 2009
Rank modulation has been recently introduced as a new information representation scheme for flash memories. Given the charge levels of a group of flash cells, sorting is used to induce a...
Provided by California Institute of Technology
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White Papers
Storage Coding For Wear Leveling in Flash Memories
Feb 2009
NAND flash memories are currently the most widely used type of flash memories. In a NAND flash memory, although a cell block consists of many pages, to rewrite one page, the whole block needs to...
Provided by Texas A&M University
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White Papers
Universal Rewriting in Constrained Memories
Apr 2009
A constrained memory is a storage device whose elements change their states under some constraints. A typical example is flash memories, in which cell levels are easy to increase but hard to...
Provided by Texas A&M University
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White Papers
Data Movement and Aggregation in Flash Memories
Jan 2010
NAND flash memories have become the most widely used type of non-volatile memories. In a NAND flash memory, every block of memory cells consists of numerous pages, and rewriting a single page...
Provided by Texas A&M University
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White Papers
Fit a Spread Estimator in Small Memory
May 2009
The spread of a source host is the number of distinct destinations that it has sent packets to during a measurement period. A spread estimator is a software/hardware module on a router that...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
The Design and Implementation of RAPID-Cache: A Reliable, Inexpensive, and High-Performance I/O Cache for Linux
Jan 2011
Most file system performance enhancing techniques, such as the I/O buffer cache and the Log-structured File Systems (LFS), relying on caching data in volatile RAM for a period of time before...
Provided by University of Cincinnati
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White Papers
Wireless Sensor Networks for Healthcare
May 2010
Driven by the confluence between the need to collect data about people's physical, physiological, psychological, cognitive, and behavioral processes in spaces ranging from personal to urban and...
Provided by Harvard University
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White Papers
Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches
Dec 2010
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory technology that is a potential universal memory that could replace SRAM in processor caches. This paper presents a novel...
Provided by University of Virginia
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White Papers
Microsearch: When Search Engines Meet Small Devices
Feb 2008
With the increasing popularity of RFID applications, different authentication schemes have been proposed to provide security and privacy protection to users. Most recent RFID protocols use a...
Provided by College of William and Mary
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White Papers
Chosen-Ciphertext Secure Fuzzy Identity-Based Key Encapsulation Without ROM
Apr 2008
The authors use hybrid encryption with Fuzzy Identity-Based Encryption (Fuzzy-IBE) schemes, and present the first and efficient Fuzzy Identity-Based Key Encapsulation Mechanism (Fuzzy-IB-KEM)...
Provided by Nanjing University of Aeronautics and Astronautics
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White Papers
Perfectly Secure Oblivious RAM Without Random Oracles
Mar 2010
In many cases it is attractive to store data at an untrusted party, and only retrieve the needed parts of it. Encryption can help ensure that the party storing the data has no idea of what he is...
Provided by University of Aarhus
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White Papers
Oblivious RAM Revisited
Jun 2010
The need to enhance the security of data storage systems and to encrypt the content they store is obvious. Various encryption algorithms are in common use for many years, so content-encryption may...
Provided by University of Haifa
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Whitepapers
Fault Tolerant Techniques for Reconfigurable Devices: A Brief Survey
Jan 2013
Reconfigurable devices are the programmable devices used to implement complex functions in applications like space missions, communication systems, nuclear systems and adaptive computing systems...
Provided by International Journal of Application or Innovation in Engineering & Management (IJAIEM)
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Whitepapers
Energy Reduction for STT-RAM Using Early Write Termination
Nov 2009
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high access speed. However, one...
Provided by Association for Computing Machinery
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Whitepapers
Enhancing Phase Change Memory Lifetime Through Fine-Grained Current Regulation and Voltage Upscaling
Aug 2011
Phase Change Memory (PCM) recently has emerged as a promising memory technology. However it suffers from limited write endurance. Recent studies have shown that the lifetime of PCM cells heavily...
Provided by Institute of Electrical & Electronic Engineers
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Whitepapers
An Efficient Static Ram Cell Design for Low Power Consumption
Mar 2012
A low power Static-Random Access Memory (SRAM) has become a critical component in modern VLSI systems. In cells, the bit-lines are the most power consuming components because of larger power...
Provided by International Journal of Communications and Engineering
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Whitepapers
ATD Circuit for Asynchronous RAM
Nov 2012
Synchronous design and Asynchronous design are two different types of memory designs. The synchronous design has to suffer from problems such as clock skew, power consumption, synchronization with...
Provided by International Journal of Emerging Technology and Advanced Engineering (IJETAE)
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Whitepapers
A Novel Approach to Use ZnO Thin Film as a Switching in Dynamic Random Access Memory (DRAM) Cell
Apr 2012
Resistance switching Random Access Memory (RRAM) has drawn considerable attention for the application in non-volatile memory element in semiconductor memory devices. A ZnO thin film now assumed to...
Provided by International Journal of Computer Applications
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Whitepapers
Design and VLSI Implementation of 8 Mb Low Power SRAM in 90nm
Jan 2009
This paper deals with the design and analysis of 8Mb Static Random Access Memory (SRAM) at 90nm, focusing on optimizing power and delay. The SRAM access path is split into two portions: from...
Provided by EuroJournals
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Whitepapers
Prefetch-Aware Memory Controllers
Oct 2011
Existing DRAM controllers employ rigid, non-adaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetches the same as demand requests, and...
Provided by Institute of Electrical & Electronic Engineers
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Whitepapers
RAIDR: Retention-Aware Intelligent DRAM Refresh
Apr 2012
Dynamic Random-Access Memory (DRAM) is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh operations waste energy...
Provided by Carnegie Mellon University
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Whitepapers
How to Garble RAM Programs
Nov 2012
Yao's Garbled Circuits is one of the central and one of the most widely used tools in cryptography, both in theory and in practice. It has numerous applications and multiple implementations, as...
Provided by University of Calgary
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Whitepapers
Design of Reversible Random Access Memory
Oct 2012
Reversible logic has become immensely popular research area and its applications have spread in various technologies for their low power consumption. In this paper, the authors proposed an...
Provided by International Journal of Computer Applications
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Whitepapers
Towards Practical Oblivious RAM
Dec 2012
As cloud computing gains momentum, an increasing amount of data is outsourced to cloud storage, and data privacy has become an important concern for many businesses and individuals alike. The...
Provided by UC AB
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Whitepapers
External Memory System Optimization for FPGABasedImplementation of Speech Signal Processing
Jul 2012
A field programmable gate array is an integrated circuit designed to be configured and implemented any logical function. Recently, the use of an FPGA becomes a suited way to implement real time...
Provided by International Association of Engineers
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Whitepapers
Design of High Speed DDR3 SDRAM Controller
Jul 2011
In computing, DDR3 SDRAM or double-data-rate three synchronous dynamic random access memories is a random access memory interface technology used for high bandwidth storage of the working data of...
Provided by International Journal of Engineering Research and Applications (IJERA)
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Whitepapers
A Buffer Management Scheme for Mobile Computers with Hybrid Main Memory and Flash Memory Storages
Apr 2012
Recently DRAM and PRAM hybrid main memory organization has been studied in order to address the high levels of energy dissipation in DRAM based main memory. It is expected that this new memory...
Provided by Science and Development Network (SciDev.Net)
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Whitepapers
Design of Low Power Double Data Rate 3 Memory Controller With AXI Compliant
Jun 2012
As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. The next generation family of Double Data Rate (DDR) RAMs are DDR3 RAM. DDR3...
Provided by International Journal of Engineering and Advanced Technology (IJEAT)
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Whitepapers
Implementation of March Algorithm Based MBIST Architecture for SRAM
May 2012
This paper presents the implementation of March Algorithm based Memory Built-In Self Test (MBIST) architecture for Static Random Access Memory (SRAM). A Finite State Machine (FSM) is designed to...
Provided by International Journal of Advanced Research in Computer Engineering & Technology
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Whitepapers
Current Mode Sense Amplifier for SRAM Memory
May 2012
The sense amplifier is one of the most important components of semiconductor memories used to sense stored date. This plays an important role to reduce the overall sensing delay and voltage....
Provided by IJERT - International Journal of Engineering Research and Technology
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Whitepapers
A High Performance DDR3 SDRAM Controller
Oct 2011
The paper presents the implementation of compliant DDR3 memory controller. It discusses the overall architecture of the DDR3 controller along with the detailed design and operation of its...
Provided by Interscience Open Access Journals
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Whitepapers
Dual-Port SDRAM Optimization With Semaphore Authority Management Controller
Feb 2010
This paper proposes the Semaphore Authority Management (SAM) controller to optimize the Dual-Port SDRAM (DPSDRAM) in the mobile multimedia systems. Recently, the DPSDRAM with a shared bank...
Provided by Electronics and Telecommunication Research Institute
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Webcasts
How to Know How Much RAM Should You Get for Your Computer
Jan 2012
In this Webcast the presenter describes about the usage of RAM in the computer. The presenter describes always get more RAM for the computer. One can never have too much RAM. Having too much RAM...
Provided by Videojug
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Whitepapers
RAMCube: Exploiting Network Proximity for RAM-Based Key-Value Store
May 2012
Disk-based storage is becoming increasingly problematic in meeting the needs of large-scale cloud applications. Recently RAM-based storage is proposed by aggregating the RAM of thousands of...
Provided by Microsoft Research
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Whitepapers
The DIMM Tree Architecture: A High Bandwidth and Scalable Memory System
Nov 2011
The demand for capacity and off-chip bandwidth to DRAM will continue to grow as the authors integrate more cores onto a die. However, as the data rate of DRAM has increased, the number of DIMMs...
Provided by Institute of Electrical & Electronic Engineers
-
Whitepapers
The Evolution of the Electronics Industry
May 2012
Transistor by transistor, the electronics industry is literally changing the world. Consider the following: today's fastest computers can now achieve 10 quadrillion operations a second1; by 2015,...
Provided by IBM
-
White Papers
Design and VLSI Implementation of DDR SDRAM Controller for High Speed Applications
Jul 2011
Synchronous DRAM (SDRAM) has become a mainstream memory of choice in design due to its speed, burst access and pipeline features. For high-end applications using processors, the interface to the...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
Method to Minimize the Clock Skew and Uniform Clock Distribution Using Parallel Port in Pipe Line Based Multi Channel DMA Request Terminal for Frequency Measurement
Jun 2010
This paper presents a new wide-range digital speed measurement method with jitter removal technique and using the Direct Memory Access (DMA) Terminal Count Register (TCR). The authors' work also...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
Design and FPGA Implementation of DDR3 SDRAM Controller for High Performance
Aug 2011
The demand for faster and cheaper memories has been increasing by the day. Hence, these memory devices are rapidly developing to give high density and high memory bandwidths. However, with the...
Provided by Academy & Industry Research Collaboration Center
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White Papers
Using Subthreshold SRAM to Design Low-Power Crypto Hardware
Aug 2011
Cryptography and Security hardware architecture designing is in essential need for efficient power utilization which is achieved earlier by giving a range of tradeoff between speed and power...
Provided by Umm Al-Qura University
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White Papers
To Reduce SRAM Sub-Threshold Leakage Using Stack and Zig-Zag Techniques
Apr 2012
The growing market of portable electronics devices demands lesser power dissipation for longer battery life and compact system. Considerable attention has been given to the design of low-power and...
Provided by International Journal of Scientific Engineering and Technology
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White Papers
Deep Sub-Micron SRAM Design for DRV Analysis and Low Leakage
Nov 2011
This paper deals with the design opportunities of Static Random Access Memory (SRAM) for lower power consumption and propagation delay. Initially, the existing SRAM architectures are investigated,...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Analysis of Leakage Reduction Technique on Different SRAM Cells
Jan 2012
Leakage components is very important for estimation and reduction of leakage power, especially for low power applications. This provides the motivation to explore the design of low leakage SRAM...
Provided by International Journal of Engineering Trends and Technology
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White Papers
Predator: A Predictable SDRAM Memory Controller
Oct 2007
Memory requirements of Intellectual Property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAMs, are shared...
Provided by Association for Computing Machinery
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White Papers
Improved Power Modeling of DDR SDRAMs
Jun 2011
Power modeling and estimation has become one of the most defining aspects in designing modern embedded systems. In this context, DDR SDRAM memories contribute significantly to system power...
Provided by Delft University of Technology
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White Papers
Automatic Generation of Efficient Predictable Memory Patterns
Jun 2011
Verifying firm real-time requirements get increasingly complex, as the number of applications in embedded systems grows. Predictable systems reduce the complexity by enabling formal verification....
Provided by Eindhoven University of Technology (TU/e)
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White Papers
Memory Controllers for High-Performance and Real-Time MPSoCs
Oct 2011
3D stacking of multi-core heterogeneous system opens a new era of architecture exploration with new partitioning of the overall System-on-Chip. After a description of the 3D stacking technologies,...
Provided by Association for Computing Machinery
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White Papers
Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations
Oct 2008
This paper examines the hardware implementation trade-offs when evaluating functions via piecewise polynomial approximations and interpolations for precisions of up to 24 bits. In polynomial...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method
Aug 2007
The authors have presented an automated methodology for producing hardware-based non-uniform RNG designs using the inversion method. The designs are capable of generating random numbers from...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Rate-Based Pacing for Optical Packet Switched Networks With Very Small Optical RAM
Aug 2007
The authors show that by applying rate-based pacing at the edge nodes, very small optical RAM buffers can be enough for high utilization and low packet drop ratio inside core Optical...
Provided by Osaka University
-
White Papers
Simple But Effective Heterogeneous Main Memory With On-Chip Memory Controller Support
Nov 2010
System-in-Package (SiP) and 3D integration are promising technologies to bring more memory onto a microprocessor package to mitigate the "Memory wall" problem. In this paper, instead of using them...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Design and Modelling of Paralleled RAM Architecture
Jan 2012
In this paper a structural approach to the design of Two-Dimensional (2D) addressing mode Static Random Access Memory (RAM) using Very High Speed Integrated Circuit Hardware Description Language...
Provided by International Association of Computer Science & Information Technology (IACSIT)
-
Whitepapers
The Evolution of the Electronics Industry
May 2012
Transistor by transistor, the electronics industry is literally changing the world. Consider the following: today's fastest computers can now achieve 10 quadrillion operations a second1; by 2015,...
Provided by IBM
-
Case Studies
Advanced Micro Devices Case Study: Bentley Systems Software
Jan 2009
With over 2,800 colleagues in over 50 offices worldwide and annual revenues surpassing $450 million, Bentley Systems has invested over $I billion in research, development and acquisitions since...
Provided by Advanced Micro Devices (AMD)
-
White Papers
Incident Response: Speed Can Mean the Difference Between Success and Failure
Nov 2009
When it comes to investigations and incident response speed is all important. The faster an examiner gets the data in a consumable form the faster an incident can be diagnosed and resolved. Even...
Provided by AccessData
-
White Papers
Redundant Optical Storage System Using DVD-RAM Library
May 2009
A Digital Virtual Disk (DVD) Random Access Memory (RAM) Redundant Array of Inexpensive Libraries (RAIL) optical storage system has been developed and tested at NTT Integrated Information & Energy...
Provided by NTT Communication Science Laboratories
-
White Papers
The Value of Using ECC Memory in Embedded Applications
Oct 2009
This paper provides an introduction to Error Correcting Code (ECC) DRAM. It discusses the risks of a system encountering random memory errors and the approaches for combating them. DRAM is...
Provided by Advanced Micro Devices
-
White Papers
Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces
Nov 2007
The DDR3 SDRAM memory architectures support higher bandwidths with bus rates of 600 Mbps to 1.6 Gbps (300 to 800 MHz), 1.5V operation for lower power, and higher densities of 2 Gbits on a 90-nm...
Provided by Altera
-
White Papers
Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance
Dec 2009
The Phase-Change Random Access Memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmability, low-power...
Provided by Association for Computing Machinery
-
Whitepapers
Storage-Class Memory: The Next Storage System Technology
Sep 2008
Maintaining the performance growth rate of the 30-yearold system memory and storage hierarchy, primarily based on DRAM (Dynamic RAM) and disks, has become a major challenge in the design of...
Provided by IBM
-
White Papers
Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores
Jun 2010
DRAM vendors have traditionally optimized the cost-per-bit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, where a single...
Provided by Association for Computing Machinery
-
White Papers
Micro-Pages: Increasing DRAM Efficiency With Locality-Aware Data Placement
Mar 2010
Power consumption and DRAM latencies are serious concerns in modern Chip-MultiProcessor (CMP or Multi-core) based compute systems. The management of the DRAM row buffer can significantly impact...
Provided by Association for Computing Machinery
-
White Papers
Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation With Application to SRAM Circuit Design
Jul 2007
Circuit reliability under statistical process variation is an area of growing concern. For highly replicated circuits such as SRAMs and flip flops, a rare statistical event for one circuit may...
Provided by Carnegie Mellon University
-
White Papers
Extended Abstract: The Butterfly PUF Protecting IP on Every FPGA
Jul 2008
IP protection of hardware designs is the most important requirement for many FPGA IP vendors. To this end, various solutions have been proposed by FPGA manufacturers based on the idea of bitstream...
Provided by Katholieke Universiteit Leuven
-
White Papers
Suitability of Requirements Abstraction Model (RAM) Requirements for High-Level System Testing
Jun 2009
The Requirements Abstraction Model (RAM) helps in managing abstraction in requirements by organizing them at four levels (product, feature, function and component). The RAM is adaptable and can be...
Provided by Katholieke Universiteit Leuven
-
White Papers
3D Network-on-Chip With On-Chip DRAM: An Empirical Analysis for Future Chip Multiprocessor
Nov 2010
With the increasing number of on-chip components and the critical requirement for processing power, Chip MultiProcessor (CMP) has gained wide acceptance in both academia and industry during the...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Low Power SRAM Base on Novel Word-Line Decoding
Jun 2009
This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to...
Provided by Islamic Azad University
-
White Papers
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
Nov 2008
Intermittently-powered applications create a need for low-cost security and privacy in potentially hostile environments, supported by primitives including identification and random number...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Design and Implementation of 8K-Bits Low Power SRAM in 180nm Technology
Mar 2009
This paper explores the tradeoffs that are involved in the design of SRAM. The major components of an SRAM such as the row decoders, the memory cells and the sense amplifiers have been studied in...
Provided by SV College of Engineering & Technology
-
White Papers
Online Memory Compression for Embedded Systems
Feb 2010
Memory is a scarce resource during embedded system design. Increasing memory often increases packaging costs, cooling costs, size, and power consumption. This paper presents CRAMES, a novel and...
Provided by Association for Computing Machinery
-
White Papers
MEMMU: Memory Expansion for MMU-Less Embedded Systems
Apr 2009
Random Access Memory (RAM) is tightly constrained in the least expensive, lowest-power embedded systems such as sensor network nodes and portable consumer electronics. The most widely used sensor...
Provided by Association for Computing Machinery
-
White Papers
Application-Aware NoC Design for Efficient SDRAM Access
Jun 2010
In many-core processors based on Networks-on-Chip (NoC), memory Quality-of-Service (QoS) becomes one of the most important issues since both memory and on-chip network are critical shared...
Provided by Association for Computing Machinery
-
White Papers
An SDRAM-Aware Router for Networks-on-Chip
Jul 2009
This paper presents a NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilization and reduce memory...
Provided by Association for Computing Machinery
-
White Papers
Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup
Jan 2008
Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of today's high-end...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM
Oct 2008
In this paper, the authors present a deep subthreshold 6-T SRAM, which was fabricated in an industrial 0.13 m CMOS technology. The authors first use detailed simulations to explore the challenges...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A 5.42nW/kB Retention Power Logic-Compatible Embedded DRAM With 2T Dual-Vt Gain Cell for Low Power Sensing Applications
Jan 2011
A logic-compatible 2T dual-Vt embedded DRAM (eDRAM) is proposed for ultra-small sensing systems to achieve 8× longer retention time, 5× lower refresh power and 30% reduced area compared with the...
Provided by University of Michigan
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White Papers
SSA - Superblock-Based Storage Architecture: A New Approach for Boosting I/O Performance
Jan 2011
Many of the new I/O architectures like DCD, RAPID cache and LFS focus on improving the disk write performance. However, many I/O intensive applications are read-dominated or generate substantial...
Provided by University of Cincinnati
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White Papers
Joint Coding for Flash Memory Storage
Apr 2008
Flash memory is an electronic non-volatile memory with wide applications. Due to the substantial impact of block erasure operations on the speed, reliability and longevity of flash memories,...
Provided by Texas A&M University
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White Papers
On the Capacity of Bounded Rank Modulation for Flash Memories
Jun 2009
Rank modulation has been recently introduced as a new information representation scheme for flash memories. Given the charge levels of a group of flash cells, sorting is used to induce a...
Provided by California Institute of Technology
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White Papers
Storage Coding For Wear Leveling in Flash Memories
Feb 2009
NAND flash memories are currently the most widely used type of flash memories. In a NAND flash memory, although a cell block consists of many pages, to rewrite one page, the whole block needs to...
Provided by Texas A&M University
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White Papers
Universal Rewriting in Constrained Memories
Apr 2009
A constrained memory is a storage device whose elements change their states under some constraints. A typical example is flash memories, in which cell levels are easy to increase but hard to...
Provided by Texas A&M University
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White Papers
Data Movement and Aggregation in Flash Memories
Jan 2010
NAND flash memories have become the most widely used type of non-volatile memories. In a NAND flash memory, every block of memory cells consists of numerous pages, and rewriting a single page...
Provided by Texas A&M University
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White Papers
Fit a Spread Estimator in Small Memory
May 2009
The spread of a source host is the number of distinct destinations that it has sent packets to during a measurement period. A spread estimator is a software/hardware module on a router that...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
The Design and Implementation of RAPID-Cache: A Reliable, Inexpensive, and High-Performance I/O Cache for Linux
Jan 2011
Most file system performance enhancing techniques, such as the I/O buffer cache and the Log-structured File Systems (LFS), relying on caching data in volatile RAM for a period of time before...
Provided by University of Cincinnati
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White Papers
Wireless Sensor Networks for Healthcare
May 2010
Driven by the confluence between the need to collect data about people's physical, physiological, psychological, cognitive, and behavioral processes in spaces ranging from personal to urban and...
Provided by Harvard University
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White Papers
Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches
Dec 2010
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory technology that is a potential universal memory that could replace SRAM in processor caches. This paper presents a novel...
Provided by University of Virginia
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White Papers
Microsearch: When Search Engines Meet Small Devices
Feb 2008
With the increasing popularity of RFID applications, different authentication schemes have been proposed to provide security and privacy protection to users. Most recent RFID protocols use a...
Provided by College of William and Mary
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White Papers
Chosen-Ciphertext Secure Fuzzy Identity-Based Key Encapsulation Without ROM
Apr 2008
The authors use hybrid encryption with Fuzzy Identity-Based Encryption (Fuzzy-IBE) schemes, and present the first and efficient Fuzzy Identity-Based Key Encapsulation Mechanism (Fuzzy-IB-KEM)...
Provided by Nanjing University of Aeronautics and Astronautics
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White Papers
Perfectly Secure Oblivious RAM Without Random Oracles
Mar 2010
In many cases it is attractive to store data at an untrusted party, and only retrieve the needed parts of it. Encryption can help ensure that the party storing the data has no idea of what he is...
Provided by University of Aarhus
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White Papers
Oblivious RAM Revisited
Jun 2010
The need to enhance the security of data storage systems and to encrypt the content they store is obvious. Various encryption algorithms are in common use for many years, so content-encryption may...
Provided by University of Haifa
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White Papers
A Comprehensive Approach to DRAM Power Management
Apr 2008
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. The authors make three contributions: The authors describe a...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
The Conquest File System: Better Performance Through a Disk/Persistent-RAM Hybrid Design
Jan 2011
Modern file systems assume the use of disk, a system-wide performance bottleneck for over a decade. Current disk caching and RAM file systems either impose high overhead to access memory content...
Provided by Association for Computing Machinery
