- Subscribe to this page:
- RSS
- Email Alert
dvd-rw - ram - rom
(136 results)-
White Papers
A Comprehensive Approach to DRAM Power Management
Apr 2008
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. The authors make three contributions: The authors describe a...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
The Conquest File System: Better Performance Through a Disk/Persistent-RAM Hybrid Design
Jan 2011
Modern file systems assume the use of disk, a system-wide performance bottleneck for over a decade. Current disk caching and RAM file systems either impose high overhead to access memory content...
Provided by Association for Computing Machinery
-
White Papers
Tri-Gate Bulk CMOS Technology for Improved SRAM Scalability
Jun 2010
A simple approach for manufacturing quasi-planar tri-gate bulk MOSFET structures is demonstrated and shown to be effective for reducing variation in 6T-SRAM read and write margins, in an early...
Provided by University of California, Berkeley
-
White Papers
Performance Evaluation of Parallel Applications on Next Generation Memory Architecture With Power-Aware Paging Method
Mar 2008
With increasing demand for low power high performance computing, reducing power of not only CPUs but also memory is becoming important. In typical general purpose HPC environments, DRAM is...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays
Apr 2010
Negative Bias Temperature Instability (NBTI) is an important lifetime reliability problem in microprocessors. SRAM-based structures within the processor are especially susceptible to NBTI since...
Provided by University of Virginia
-
White Papers
Extending the Effectiveness of 3D-Stacked DRAM Caches With an Adaptive Multi-Queue Policy
Dec 2009
3D-integration is a promising technology to help combat the "MemoryWall" in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level cache (LLC). While...
Provided by Association for Computing Machinery
-
White Papers
3D-Stacked Memory Architectures for Multi-Core Processors
Jun 2008
Three-dimensional integration enables stacking memory directly on top of a microprocessor, thereby significantly reducing wire delay between the two. Previous studies have examined the performance...
Provided by Georgia Institute of Technology
-
White Papers
Shipping to Streaming: Is This Shift Green?
Aug 2010
Streaming movies over the Internet has become increasingly popular in recent years as an alternative to mailing DVDs to a customer. In this paper the authors investigate the environmental- and...
Provided by Association for Computing Machinery
-
White Papers
Delay-Hiding Energy Management Mechanisms for DRAM
Feb 2010
Current trends in data-intensive applications increase the demand for larger physical memory, resulting in the memory subsystem consuming a significant portion of system's energy. Furthermore,...
Provided by University of Arizona
-
White Papers
Eliminating the Call Stack to Save RAM
Jun 2009
Most programming languages support a call stack in the programming model and also in the runtime system. The authors show that for applications targeting low-power embedded microcontrollers...
Provided by Association for Computing Machinery
-
White Papers
SSDAlloc: Hybrid SSD/RAM Memory Management Made Easy
Mar 2011
The authors introduce SSDAlloc, a hybrid main memory management system that allows developers to treat Solid-State Disk (SSD) as an extension of the RAM in a system. SSDAlloc moves the SSD upward...
Provided by Princeton University
-
White Papers
Accelerating Search and Recognition With a TCAM Functional Unit
Apr 2008
World data is increasing rapidly, doubling almost every three years. To comprehend and use this data effectively, Search and Recognition (SR) applications will demand more computational power in...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
On the Cost of Concurrency in Transactional Memory
Mar 2011
The crux of Software Transactional Memory (STM) is to combine an easy-to-use programming interface with an efficient utilization of the concurrent computing abilities provided by modern machines....
Provided by Cornell University
-
White Papers
Compressed Random Access Memory
Nov 2010
Motivated by applications which need to store huge amounts of data in the main memory of a computer, this paper proposes a new dynamic data-structure for compressed random access memory. Ferragina...
Provided by Ochanomizu University
-
White Papers
Guiding Architectural SRAM Models
Jan 2011
Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Making good...
Provided by University of California
-
White Papers
High-Bandwidth Network Memory System Through Virtual Pipelines
Apr 2010
As network bandwidth increases, designing an effective memory system for network processors becomes a significant challenge. The size of the routing tables, the complexity of the packet...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Tree Indexing on Solid State Drives
Oct 2009
Large flash disks, or Solid State Drives (SSDs), have become an attractive alternative to magnetic hard disks, due to their high random read performance, low energy consumption and other features....
Provided by VLDB Endowment
-
White Papers
A Study on RAM Requirements of Various SHA-3 Candidates on Low-Cost 8-Bit CPUs
May 2009
In this paper, the authors compare the implementation costs of various SHA-3 candidates on low-cost 8-bit CPUs by estimating RAM/ROM requirements of them. As a first step toward this kind of...
Provided by Katholieke Universiteit Leuven
-
White Papers
Forwardflow: Scalable, RAM-Based Dataflow Execution
Sep 2009
Power (and thermal) limits have forced an industry-wide shift from increasingly complex uniprocessors to multicore chips with 4, 8, and even 16 simpler processor cores. Yet Amdahl's Law suggests...
Provided by University of Wisconsin System
-
White Papers
FlashStore: High Throughput Persistent KeyValue Store
Aug 2010
The authors present FlashStore, a high throughput persistent keyvalue store that uses flash memory as a non-volatile cache between RAM and hard disk. FlashStore is designed to store the working...
Provided by VLDB Endowment
-
White Papers
PRISM: Zooming in Persistent RAM Storage Behavior
Feb 2011
It has been foreseen that some of the roles assumed by conventional rotating Hard Disk Drives (HDDs) will migrate to Solid-State Drives (SSDs) and emerging persistent RAM storages. New persistent...
Provided by University of Pittsburgh
-
White Papers
Perspectives on Transactional Memory
Jun 2009
The authors examine the role of transactional memory from two perspectives: That of a programming language with atomic actions and that of implementations of the language. They argue that it is...
Provided by University of California
-
White Papers
A Model of Dynamic Separation for Transactional Memory
Jul 2009
Dynamic separation is a new programming discipline for systems with transactional memory. The authors study it formally in the setting of a small calculus with transactions. They provide a precise...
Provided by University of California
-
White Papers
SPM Management Using Markov Chain Based Data Access Prediction
Jul 2008
Leveraging the power of ScratchPad Memories (SPMs) available in most embedded systems today is crucial to extract maximum performance from application programs. While regular accesses like scalar...
Provided by Syracuse University
-
White Papers
Fast Multiplication of Large Permutations for Disk, Flash Memory and RAM
Jul 2010
Permutation multiplication (or permutation composition) is perhaps the simplest of all algorithms in computer science. Yet for large permutations, the standard algorithm is not the fastest for...
Provided by Association for Computing Machinery
-
White Papers
Optimal Speedup on a Low-Degree Multi-Core Parallel Architecture (LoPRAM)
Jan 2011
Modern microprocessor architectures have gradually incorporated support for parallelism. In the past the degree of parallelism was rather small and as such it could be best modeled as a constant...
Provided by University of Waterloo
-
White Papers
Should We Worry About Memory Loss?
Apr 2011
In recent years the High Performance Computing (HPC) industry has benefited from the development of higher density multi-core processors. With recent chips capable of executing up to 32 tasks in...
Provided by University of Warwick
-
White Papers
Analyzing the Impact of Useless Write-Backs on the Endurance and Energy Consumption of PCM Main Memory
Feb 2011
Phase Change Memory (PCM) is an emerging technology that has been recently considered as a cost-effective and energy-efficient alternative to traditional DRAM main memory. Due to the high energy...
Provided by University of Pittsburgh
-
White Papers
Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories
Jan 2011
Non-volatile memories, such as Flash and Phase-Change Memory, are replacing other memory and storage technologies. Although these new technologies have desirable energy and scalability properties,...
Provided by European Design and Automation Association
-
White Papers
Fast Crash Recovery in RAMCloud
Mar 2011
RAMCloud is a DRAM-based storage system that provides inexpensive durability and availability by recovering quickly after crashes, rather than storing replicas in DRAM. RAMCloud scatters backup...
Provided by Stanford University
-
White Papers
The Case for RAMClouds: Scalable High-Performance Storage Entirely in DRAM
Dec 2009
Disk-oriented approaches to online storage are becoming increasingly problematic: they do not scale gracefully to meet the needs of large-scale Web applications, and improvements in disk capacity...
Provided by Stanford University
-
White Papers
Bandwidth, Area Efficient and Target Device Independent DDR SDRAM Controller
Jun 2009
The application of the Synchronous Dynamic Random Access Memory (SDRAM) has gone beyond the scope of personal computers for quite a long time. It comes into hand whenever a big amount of low price...
Provided by Gwangju Institute of Science and Technology
-
White Papers
Litearch: An Energy-Centric Software Architecture for Wireless Sensor Networks
Oct 2008
Wireless sensor networks promise an unprecedented potential for observing the physical world. Their battery life, however, is usually the bottleneck that limits application lifetime, a problem...
Provided by University of Illinois
-
White Papers
Active Memory Operations
Jun 2007
The performance of modern microprocessors is increasingly limited by their inability to hide main memory latency. The problem is worse in large-scale shared memory systems, where remote memory...
Provided by Association for Computing Machinery
-
White Papers
Making DRAM Refresh Predictable
May 2010
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Schedulability theory...
Provided by North Carolina State University
-
White Papers
MemScale: Active Low-Power Modes for Main Memory
Mar 2011
Main memory is responsible for a large and increasing fraction of the energy consumed by servers. Prior work has focused on exploiting DRAM low-power states to conserve energy. However, these...
Provided by Association for Computing Machinery
-
White Papers
TID Damage and Annealing Response of 90 Nm Commercial-Density SRAMs
Sep 2008
The authors characterize the TID resilience and annealing response of high-density SRAMs, fabricated in 90 nm commercial processes. Results demonstrate intrinsic SRAM hardness at 300 krad(Si), but...
Provided by University of Southern California
-
White Papers
Reliable Adaptable Network RAM
Jul 2008
The authors present reliability solutions for adaptable Network RAM systems running on general-purpose clusters. Network RAM allows nodes with over-committed memory to swap pages over the network,...
Provided by Swarthmore College
-
White Papers
Rethinking Database Algorithms for Phase Change Memory
Jan 2011
Phase Change Memory (PCM) is an emerging memory technology with many attractive features: it is non-volatile, byte-addressable, 2 - 4X denser than DRAM, and orders of magnitude better than NAND...
Provided by Intel
-
White Papers
MCCDB: Minimizing Cache Conflicts in Multi-Core Processors for Databases
Aug 2009
In a typical commercial multi-core processor, the Last Level Cache (LLC) is shared by two or more cores. Existing studies have shown that the shared LLC is beneficial to concurrent query processes...
Provided by VLDB Endowment
-
White Papers
Re-Architecting DRAM Memory Systems With Monolithically Integrated Silicon Photonics
Jun 2010
The performance of future many-core processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of electrical DRAM...
Provided by Association for Computing Machinery
-
White Papers
Sparse Indexing: Large Scale, Inline Deduplication Using Sampling and Locality
Jan 2009
The authors present sparse indexing, a technique that uses sampling and exploits the inherent locality within backup streams to solve for large-scale backup (e.g., hundreds of terabytes) the...
Provided by University of California
-
White Papers
Handheld System Energy Reduction by OS-Driven Refresh
Dec 2009
Emerging portable devices relay on DRAM/flash memory system to satisfy requirements on fast and large data storage and low-energy consumption. This paper presents a novel approach to reduce energy...
Provided by Springer Science+Business Media
-
White Papers
Reducing Energy of DRAM/Flash Memory System by OS-Controlled Data Refresh
Jun 2007
This paper presents a new approach to reduce energy consumption of DRAM/flash memory system by lowering the frequency of DRAM refreshes. The approach is based on two ideas: a DRAM based swap-cache...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Hardware Efficient Approach for Memoryless-Based Multiplication and Its Application to FIR Filter
Nov 2011
In conventional memory-based multiplication design, the multiplier is replaced by a read only memory (ROM). Since the memory size increases exponentially with the input length, in this paper, a...
Provided by Academy Publisher
-
White Papers
An Approach for Adaptive DRAM Temperature and Power Management
Jun 2008
With rising capacities and higher accessing frequencies, high-performance DRAMs are providing increasing memory access bandwidth to the processors. However, the increasing DRAM performance comes...
Provided by Association for Computing Machinery
-
White Papers
Hardware/Software Techniques for DRAM Thermal Management
Dec 2010
The performance of the main memory is an important factor on overall system performance. To improve DRAM performance, designers have been increasing chip densities and the number of memory...
Provided by Northwestern University
-
White Papers
Multijunction Fault-Tolerance Architecture for Nanoscale Crossbar Memories
Mar 2008
Nanoscale elements are fabricated using bottom-up processes, and as such are prone to high levels of defects. Therefore, fault-tolerance is crucial for the realization of practical nanoscale...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Two-Tier Bloom Filter to Achieve Faster Membership Testing
Mar 2008
Bloom filters are widely used with many applications in the domain of networks. One application of interest is representing large file lists; for example lists of shared files in servers or caches...
Provided by University of South Florida
-
White Papers
Application of Nanojunction-Based RRAM to Reconfigurable IC
Aug 2008
In this paper, a novel reconfigurable architecture, rFPGA, is developed by utilizing high-density resistive memory (RRAM) circuits as FPGA components. Different from the existing CMOS-nano hybrid...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Software Approach to Unifying Multicore Caches
Jun 2011
Multicore chips will have large amounts of fast on-chip cache memory, along with relatively slow DRAM interfaces. The on-chip cache memory, however, will be fragmented and spread over the chip;...
Provided by Massachusetts Institute of Technology
-
Webcasts
Webcast: Ubuntu Cloud
Nov 2011
After years of development and fine tuning, the cloud vision of true computing elasticity is finally a reality. The question now is how organizations can best take advantage of the latest cloud...
Provided by Canonical Ltd
-
White Papers
A DRAM Centric NoC Architecture and Topology Design Approach
Apr 2011
Most communication traffic in today's System on Chips (SoC) is DRAM centric. The NoC should be designed to efficiently handle the many-to-one communication pattern, funneling to and from the DRAM...
Provided by University of Bologna
-
Whitepapers
Top 10 questions about Ubuntu Server Edition
Jul 2011
What's different about Ubuntu Server? Is it secure enough to use in my business? Will it work on my hardware? Whether you've already deployed Ubuntu in your business or are just starting to...
Provided by Canonical Ltd
-
White Papers
On Avoiding Spare Aborts in Transactional Memory
Aug 2009
This paper takes a step toward developing a theory for understanding aborts in Transactional Memory systems (TMs). Existing TMs may abort many transactions that could, in fact, commit without...
Provided by Association for Computing Machinery
-
White Papers
SMV: Selective Multi-Versioning STM
Mar 2010
The authors present Selective Multi-Versioning (SMV), a new STM that reduces the number of aborts, especially those of long read-only transactions. SMV keeps old object versions as long as they...
Provided by Technion - Israel Institute of Technology
-
White Papers
Run-Time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration
Jun 2009
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, the authors propose to use Direct Memory Access (DMA),...
Provided by KTH - Royal Institute of Technology
-
White Papers
Delay and Energy Consumption Analysis of Conventional SRAM
May 2010
The energy consumption and delay in read/write operation of conventional SRAM is investigated analytically as well as by simulation. Explicit analytical expressions for the energy consumption and...
Provided by Islamic Azad University
-
White Papers
DRAM Errors in the Wild: A Large-Scale Field Study
Jun 2009
Errors in Dynamic Random Access Memory (DRAM) are a common form of hardware failure in modern compute clusters. Failures are costly both in terms of hardware replacement costs and service...
Provided by Association for Computing Machinery
-
White Papers
MCCDB: Minimizing Cache Conflicts in Multi-Core Processors for Databases
Aug 2009
In a typical commercial multi-core processor, the Last Level Cache (LLC) is shared by two or more cores. Existing studies have shown that the shared LLC is beneficial to concurrent query processes...
Provided by VLDB Endowment
-
White Papers
Rethinking Database Algorithms for Phase Change Memory
Jan 2011
Phase Change Memory (PCM) is an emerging memory technology with many attractive features: it is non-volatile, byte-addressable, 2 - 4X denser than DRAM, and orders of magnitude better than NAND...
Provided by Intel
-
White Papers
Reliable Adaptable Network RAM
Jul 2008
The authors present reliability solutions for adaptable Network RAM systems running on general-purpose clusters. Network RAM allows nodes with over-committed memory to swap pages over the network,...
Provided by Swarthmore College
-
White Papers
TID Damage and Annealing Response of 90 Nm Commercial-Density SRAMs
Sep 2008
The authors characterize the TID resilience and annealing response of high-density SRAMs, fabricated in 90 nm commercial processes. Results demonstrate intrinsic SRAM hardness at 300 krad(Si), but...
Provided by University of Southern California
-
White Papers
MemScale: Active Low-Power Modes for Main Memory
Mar 2011
Main memory is responsible for a large and increasing fraction of the energy consumed by servers. Prior work has focused on exploiting DRAM low-power states to conserve energy. However, these...
Provided by Association for Computing Machinery
-
White Papers
Making DRAM Refresh Predictable
May 2010
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Schedulability theory...
Provided by North Carolina State University
-
White Papers
Active Memory Operations
Jun 2007
The performance of modern microprocessors is increasingly limited by their inability to hide main memory latency. The problem is worse in large-scale shared memory systems, where remote memory...
Provided by Association for Computing Machinery
-
White Papers
Litearch: An Energy-Centric Software Architecture for Wireless Sensor Networks
Oct 2008
Wireless sensor networks promise an unprecedented potential for observing the physical world. Their battery life, however, is usually the bottleneck that limits application lifetime, a problem...
Provided by University of Illinois
-
White Papers
Bandwidth, Area Efficient and Target Device Independent DDR SDRAM Controller
Jun 2009
The application of the Synchronous Dynamic Random Access Memory (SDRAM) has gone beyond the scope of personal computers for quite a long time. It comes into hand whenever a big amount of low price...
Provided by Gwangju Institute of Science and Technology
-
White Papers
The Case for RAMClouds: Scalable High-Performance Storage Entirely in DRAM
Dec 2009
Disk-oriented approaches to online storage are becoming increasingly problematic: they do not scale gracefully to meet the needs of large-scale Web applications, and improvements in disk capacity...
Provided by Stanford University
-
White Papers
Fast Crash Recovery in RAMCloud
Mar 2011
RAMCloud is a DRAM-based storage system that provides inexpensive durability and availability by recovering quickly after crashes, rather than storing replicas in DRAM. RAMCloud scatters backup...
Provided by Stanford University
-
White Papers
Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories
Jan 2011
Non-volatile memories, such as Flash and Phase-Change Memory, are replacing other memory and storage technologies. Although these new technologies have desirable energy and scalability properties,...
Provided by European Design and Automation Association
-
White Papers
Analyzing the Impact of Useless Write-Backs on the Endurance and Energy Consumption of PCM Main Memory
Feb 2011
Phase Change Memory (PCM) is an emerging technology that has been recently considered as a cost-effective and energy-efficient alternative to traditional DRAM main memory. Due to the high energy...
Provided by University of Pittsburgh
-
White Papers
Should We Worry About Memory Loss?
Apr 2011
In recent years the High Performance Computing (HPC) industry has benefited from the development of higher density multi-core processors. With recent chips capable of executing up to 32 tasks in...
Provided by University of Warwick
-
White Papers
Optimal Speedup on a Low-Degree Multi-Core Parallel Architecture (LoPRAM)
Jan 2011
Modern microprocessor architectures have gradually incorporated support for parallelism. In the past the degree of parallelism was rather small and as such it could be best modeled as a constant...
Provided by University of Waterloo
-
White Papers
Fast Multiplication of Large Permutations for Disk, Flash Memory and RAM
Jul 2010
Permutation multiplication (or permutation composition) is perhaps the simplest of all algorithms in computer science. Yet for large permutations, the standard algorithm is not the fastest for...
Provided by Association for Computing Machinery
-
White Papers
SPM Management Using Markov Chain Based Data Access Prediction
Jul 2008
Leveraging the power of ScratchPad Memories (SPMs) available in most embedded systems today is crucial to extract maximum performance from application programs. While regular accesses like scalar...
Provided by Syracuse University
-
White Papers
A Model of Dynamic Separation for Transactional Memory
Jul 2009
Dynamic separation is a new programming discipline for systems with transactional memory. The authors study it formally in the setting of a small calculus with transactions. They provide a precise...
Provided by University of California
-
White Papers
Perspectives on Transactional Memory
Jun 2009
The authors examine the role of transactional memory from two perspectives: That of a programming language with atomic actions and that of implementations of the language. They argue that it is...
Provided by University of California
-
White Papers
PRISM: Zooming in Persistent RAM Storage Behavior
Feb 2011
It has been foreseen that some of the roles assumed by conventional rotating Hard Disk Drives (HDDs) will migrate to Solid-State Drives (SSDs) and emerging persistent RAM storages. New persistent...
Provided by University of Pittsburgh
-
White Papers
FlashStore: High Throughput Persistent KeyValue Store
Aug 2010
The authors present FlashStore, a high throughput persistent keyvalue store that uses flash memory as a non-volatile cache between RAM and hard disk. FlashStore is designed to store the working...
Provided by VLDB Endowment
-
White Papers
Tri-Gate Bulk CMOS Technology for Improved SRAM Scalability
Jun 2010
A simple approach for manufacturing quasi-planar tri-gate bulk MOSFET structures is demonstrated and shown to be effective for reducing variation in 6T-SRAM read and write margins, in an early...
Provided by University of California, Berkeley
-
White Papers
Performance Evaluation of Parallel Applications on Next Generation Memory Architecture With Power-Aware Paging Method
Mar 2008
With increasing demand for low power high performance computing, reducing power of not only CPUs but also memory is becoming important. In typical general purpose HPC environments, DRAM is...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays
Apr 2010
Negative Bias Temperature Instability (NBTI) is an important lifetime reliability problem in microprocessors. SRAM-based structures within the processor are especially susceptible to NBTI since...
Provided by University of Virginia
-
White Papers
Extending the Effectiveness of 3D-Stacked DRAM Caches With an Adaptive Multi-Queue Policy
Dec 2009
3D-integration is a promising technology to help combat the "MemoryWall" in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level cache (LLC). While...
Provided by Association for Computing Machinery
-
White Papers
3D-Stacked Memory Architectures for Multi-Core Processors
Jun 2008
Three-dimensional integration enables stacking memory directly on top of a microprocessor, thereby significantly reducing wire delay between the two. Previous studies have examined the performance...
Provided by Georgia Institute of Technology
-
White Papers
Shipping to Streaming: Is This Shift Green?
Aug 2010
Streaming movies over the Internet has become increasingly popular in recent years as an alternative to mailing DVDs to a customer. In this paper the authors investigate the environmental- and...
Provided by Association for Computing Machinery
-
White Papers
Delay-Hiding Energy Management Mechanisms for DRAM
Feb 2010
Current trends in data-intensive applications increase the demand for larger physical memory, resulting in the memory subsystem consuming a significant portion of system's energy. Furthermore,...
Provided by University of Arizona
-
White Papers
Eliminating the Call Stack to Save RAM
Jun 2009
Most programming languages support a call stack in the programming model and also in the runtime system. The authors show that for applications targeting low-power embedded microcontrollers...
Provided by Association for Computing Machinery
-
White Papers
SSDAlloc: Hybrid SSD/RAM Memory Management Made Easy
Mar 2011
The authors introduce SSDAlloc, a hybrid main memory management system that allows developers to treat Solid-State Disk (SSD) as an extension of the RAM in a system. SSDAlloc moves the SSD upward...
Provided by Princeton University
-
White Papers
Accelerating Search and Recognition With a TCAM Functional Unit
Apr 2008
World data is increasing rapidly, doubling almost every three years. To comprehend and use this data effectively, Search and Recognition (SR) applications will demand more computational power in...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
On the Cost of Concurrency in Transactional Memory
Mar 2011
The crux of Software Transactional Memory (STM) is to combine an easy-to-use programming interface with an efficient utilization of the concurrent computing abilities provided by modern machines....
Provided by Cornell University
-
White Papers
Compressed Random Access Memory
Nov 2010
Motivated by applications which need to store huge amounts of data in the main memory of a computer, this paper proposes a new dynamic data-structure for compressed random access memory. Ferragina...
Provided by Ochanomizu University
-
White Papers
Guiding Architectural SRAM Models
Jan 2011
Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Making good...
Provided by University of California
-
White Papers
High-Bandwidth Network Memory System Through Virtual Pipelines
Apr 2010
As network bandwidth increases, designing an effective memory system for network processors becomes a significant challenge. The size of the routing tables, the complexity of the packet...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Tree Indexing on Solid State Drives
Oct 2009
Large flash disks, or Solid State Drives (SSDs), have become an attractive alternative to magnetic hard disks, due to their high random read performance, low energy consumption and other features....
Provided by VLDB Endowment
-
White Papers
A Study on RAM Requirements of Various SHA-3 Candidates on Low-Cost 8-Bit CPUs
May 2009
In this paper, the authors compare the implementation costs of various SHA-3 candidates on low-cost 8-bit CPUs by estimating RAM/ROM requirements of them. As a first step toward this kind of...
Provided by Katholieke Universiteit Leuven
-
White Papers
Forwardflow: Scalable, RAM-Based Dataflow Execution
Sep 2009
Power (and thermal) limits have forced an industry-wide shift from increasingly complex uniprocessors to multicore chips with 4, 8, and even 16 simpler processor cores. Yet Amdahl's Law suggests...
Provided by University of Wisconsin System
-
White Papers
FlashStore: High Throughput Persistent KeyValue Store
Aug 2010
The authors present FlashStore, a high throughput persistent keyvalue store that uses flash memory as a non-volatile cache between RAM and hard disk. FlashStore is designed to store the working...
Provided by VLDB Endowment
-
White Papers
PRISM: Zooming in Persistent RAM Storage Behavior
Feb 2011
It has been foreseen that some of the roles assumed by conventional rotating Hard Disk Drives (HDDs) will migrate to Solid-State Drives (SSDs) and emerging persistent RAM storages. New persistent...
Provided by University of Pittsburgh
-
White Papers
Perspectives on Transactional Memory
Jun 2009
The authors examine the role of transactional memory from two perspectives: That of a programming language with atomic actions and that of implementations of the language. They argue that it is...
Provided by University of California
-
White Papers
A Model of Dynamic Separation for Transactional Memory
Jul 2009
Dynamic separation is a new programming discipline for systems with transactional memory. The authors study it formally in the setting of a small calculus with transactions. They provide a precise...
Provided by University of California
-
White Papers
SPM Management Using Markov Chain Based Data Access Prediction
Jul 2008
Leveraging the power of ScratchPad Memories (SPMs) available in most embedded systems today is crucial to extract maximum performance from application programs. While regular accesses like scalar...
Provided by Syracuse University
-
White Papers
Fast Multiplication of Large Permutations for Disk, Flash Memory and RAM
Jul 2010
Permutation multiplication (or permutation composition) is perhaps the simplest of all algorithms in computer science. Yet for large permutations, the standard algorithm is not the fastest for...
Provided by Association for Computing Machinery
-
White Papers
Optimal Speedup on a Low-Degree Multi-Core Parallel Architecture (LoPRAM)
Jan 2011
Modern microprocessor architectures have gradually incorporated support for parallelism. In the past the degree of parallelism was rather small and as such it could be best modeled as a constant...
Provided by University of Waterloo
-
White Papers
Should We Worry About Memory Loss?
Apr 2011
In recent years the High Performance Computing (HPC) industry has benefited from the development of higher density multi-core processors. With recent chips capable of executing up to 32 tasks in...
Provided by University of Warwick
-
White Papers
Analyzing the Impact of Useless Write-Backs on the Endurance and Energy Consumption of PCM Main Memory
Feb 2011
Phase Change Memory (PCM) is an emerging technology that has been recently considered as a cost-effective and energy-efficient alternative to traditional DRAM main memory. Due to the high energy...
Provided by University of Pittsburgh
-
White Papers
Impact of Process Variation on Endurance Algorithms for Wear-Prone Memories
Jan 2011
Non-volatile memories, such as Flash and Phase-Change Memory, are replacing other memory and storage technologies. Although these new technologies have desirable energy and scalability properties,...
Provided by European Design and Automation Association
-
White Papers
Fast Crash Recovery in RAMCloud
Mar 2011
RAMCloud is a DRAM-based storage system that provides inexpensive durability and availability by recovering quickly after crashes, rather than storing replicas in DRAM. RAMCloud scatters backup...
Provided by Stanford University
-
White Papers
The Case for RAMClouds: Scalable High-Performance Storage Entirely in DRAM
Dec 2009
Disk-oriented approaches to online storage are becoming increasingly problematic: they do not scale gracefully to meet the needs of large-scale Web applications, and improvements in disk capacity...
Provided by Stanford University
-
White Papers
Bandwidth, Area Efficient and Target Device Independent DDR SDRAM Controller
Jun 2009
The application of the Synchronous Dynamic Random Access Memory (SDRAM) has gone beyond the scope of personal computers for quite a long time. It comes into hand whenever a big amount of low price...
Provided by Gwangju Institute of Science and Technology
-
White Papers
Litearch: An Energy-Centric Software Architecture for Wireless Sensor Networks
Oct 2008
Wireless sensor networks promise an unprecedented potential for observing the physical world. Their battery life, however, is usually the bottleneck that limits application lifetime, a problem...
Provided by University of Illinois
-
White Papers
Active Memory Operations
Jun 2007
The performance of modern microprocessors is increasingly limited by their inability to hide main memory latency. The problem is worse in large-scale shared memory systems, where remote memory...
Provided by Association for Computing Machinery
-
White Papers
Making DRAM Refresh Predictable
May 2010
Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Schedulability theory...
Provided by North Carolina State University
-
White Papers
MemScale: Active Low-Power Modes for Main Memory
Mar 2011
Main memory is responsible for a large and increasing fraction of the energy consumed by servers. Prior work has focused on exploiting DRAM low-power states to conserve energy. However, these...
Provided by Association for Computing Machinery
-
White Papers
TID Damage and Annealing Response of 90 Nm Commercial-Density SRAMs
Sep 2008
The authors characterize the TID resilience and annealing response of high-density SRAMs, fabricated in 90 nm commercial processes. Results demonstrate intrinsic SRAM hardness at 300 krad(Si), but...
Provided by University of Southern California
-
White Papers
Reliable Adaptable Network RAM
Jul 2008
The authors present reliability solutions for adaptable Network RAM systems running on general-purpose clusters. Network RAM allows nodes with over-committed memory to swap pages over the network,...
Provided by Swarthmore College
-
White Papers
Rethinking Database Algorithms for Phase Change Memory
Jan 2011
Phase Change Memory (PCM) is an emerging memory technology with many attractive features: it is non-volatile, byte-addressable, 2 - 4X denser than DRAM, and orders of magnitude better than NAND...
Provided by Intel
-
White Papers
MCCDB: Minimizing Cache Conflicts in Multi-Core Processors for Databases
Aug 2009
In a typical commercial multi-core processor, the Last Level Cache (LLC) is shared by two or more cores. Existing studies have shown that the shared LLC is beneficial to concurrent query processes...
Provided by VLDB Endowment
-
White Papers
DRAM Errors in the Wild: A Large-Scale Field Study
Jun 2009
Errors in Dynamic Random Access Memory (DRAM) are a common form of hardware failure in modern compute clusters. Failures are costly both in terms of hardware replacement costs and service...
Provided by Association for Computing Machinery
-
White Papers
Delay and Energy Consumption Analysis of Conventional SRAM
May 2010
The energy consumption and delay in read/write operation of conventional SRAM is investigated analytically as well as by simulation. Explicit analytical expressions for the energy consumption and...
Provided by Islamic Azad University
