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(129 results)-
Automating Infrastructure and Operations Management with VMware
With VMware, virtualization tools come with a management system built in. Check out this webcast to learn more.
Sponsored by VMware Date: Wed, 10 Feb 2010 00:00:00 -0800
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Webcasts
Webcast: Ubuntu Cloud
Nov 2011
After years of development and fine tuning, the cloud vision of true computing elasticity is finally a reality. The question now is how organizations can best take advantage of the latest cloud...
Provided by Canonical Ltd
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White Papers
Top 10 questions about Ubuntu Server Edition
Jul 2011
What's different about Ubuntu Server? Is it secure enough to use in my business? Will it work on my hardware? Whether you've already deployed Ubuntu in your business or are just starting to...
Provided by Canonical Ltd
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White Papers
The Evolution of the Electronics Industry
May 2012
Transistor by transistor, the electronics industry is literally changing the world. Consider the following: today's fastest computers can now achieve 10 quadrillion operations a second1; by 2015,...
Provided by IBM
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Case Studies
Advanced Micro Devices Case Study: Bentley Systems Software
Jan 2009
With over 2,800 colleagues in over 50 offices worldwide and annual revenues surpassing $450 million, Bentley Systems has invested over $I billion in research, development and acquisitions since...
Provided by Advanced Micro Devices (AMD)
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White Papers
Incident Response: Speed Can Mean the Difference Between Success and Failure
Nov 2009
When it comes to investigations and incident response speed is all important. The faster an examiner gets the data in a consumable form the faster an incident can be diagnosed and resolved. Even...
Provided by AccessData
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White Papers
Redundant Optical Storage System Using DVD-RAM Library
May 2009
A Digital Virtual Disk (DVD) Random Access Memory (RAM) Redundant Array of Inexpensive Libraries (RAIL) optical storage system has been developed and tested at NTT Integrated Information & Energy...
Provided by NTT Communication Science Laboratories
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White Papers
The Value of Using ECC Memory in Embedded Applications
Oct 2009
This paper provides an introduction to Error Correcting Code (ECC) DRAM. It discusses the risks of a system encountering random memory errors and the approaches for combating them. DRAM is...
Provided by Advanced Micro Devices
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White Papers
Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces
Nov 2007
The DDR3 SDRAM memory architectures support higher bandwidths with bus rates of 600 Mbps to 1.6 Gbps (300 to 800 MHz), 1.5V operation for lower power, and higher densities of 2 Gbits on a 90-nm...
Provided by Altera
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White Papers
CA-RAM: A High-PerformanceMemory Substrate for Search-Intensive Applications
Feb 2007
This paper proposes a specialized memory structure called CA-RAM (Content Addressable Random Access Memory) to accelerate search operations present in many important real-world applications....
Provided by University of Pittsburgh
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White Papers
Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance
Dec 2009
The Phase-Change Random Access Memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmability, low-power...
Provided by Association for Computing Machinery
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White Papers
Storage-Class Memory: The Next Storage System Technology
Sep 2008
Maintaining the performance growth rate of the 30-yearold system memory and storage hierarchy, primarily based on DRAM (Dynamic RAM) and disks, has become a major challenge in the design of...
Provided by IBM
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White Papers
Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores
Jun 2010
DRAM vendors have traditionally optimized the cost-per-bit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, where a single...
Provided by Association for Computing Machinery
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White Papers
Micro-Pages: Increasing DRAM Efficiency With Locality-Aware Data Placement
Mar 2010
Power consumption and DRAM latencies are serious concerns in modern Chip-MultiProcessor (CMP or Multi-core) based compute systems. The management of the DRAM row buffer can significantly impact...
Provided by Association for Computing Machinery
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White Papers
Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM
Jun 2006
Measurements of an off-the-shelf DRAM chip confirm that different cells retain information for different amounts of time. This result extends to DRAM rows, or pages (Retention time of a page is...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation With Application to SRAM Circuit Design
Jul 2007
Circuit reliability under statistical process variation is an area of growing concern. For highly replicated circuits such as SRAMs and flip flops, a rare statistical event for one circuit may...
Provided by Carnegie Mellon University
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White Papers
Extended Abstract: The Butterfly PUF Protecting IP on Every FPGA
Jul 2008
IP protection of hardware designs is the most important requirement for many FPGA IP vendors. To this end, various solutions have been proposed by FPGA manufacturers based on the idea of bitstream...
Provided by Katholieke Universiteit Leuven
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White Papers
Suitability of Requirements Abstraction Model (RAM) Requirements for High-Level System Testing
Jun 2009
The Requirements Abstraction Model (RAM) helps in managing abstraction in requirements by organizing them at four levels (product, feature, function and component). The RAM is adaptable and can be...
Provided by Katholieke Universiteit Leuven
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White Papers
3D Network-on-Chip With On-Chip DRAM: An Empirical Analysis for Future Chip Multiprocessor
Nov 2010
With the increasing number of on-chip components and the critical requirement for processing power, Chip MultiProcessor (CMP) has gained wide acceptance in both academia and industry during the...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A Low Power SRAM Base on Novel Word-Line Decoding
Jun 2009
This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to...
Provided by Islamic Azad University
-
White Papers
Fundamental Redundancy Versus Power Trade-Off in Standby SRAM
Jan 2007
The authors study the problem of reducing power during data-retention in a standby Static Random Access Memory (SRAM). For successful data-retention, the supply voltage of an SRAM cell should be...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
Nov 2008
Intermittently-powered applications create a need for low-cost security and privacy in potentially hostile environments, supported by primitives including identification and random number...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Design and Implementation of 8K-Bits Low Power SRAM in 180nm Technology
Mar 2009
This paper explores the tradeoffs that are involved in the design of SRAM. The major components of an SRAM such as the row decoders, the memory cells and the sense amplifiers have been studied in...
Provided by SV College of Engineering & Technology
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White Papers
Online Memory Compression for Embedded Systems
Feb 2010
Memory is a scarce resource during embedded system design. Increasing memory often increases packaging costs, cooling costs, size, and power consumption. This paper presents CRAMES, a novel and...
Provided by Association for Computing Machinery
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White Papers
MEMMU: Memory Expansion for MMU-Less Embedded Systems
Apr 2009
Random Access Memory (RAM) is tightly constrained in the least expensive, lowest-power embedded systems such as sensor network nodes and portable consumer electronics. The most widely used sensor...
Provided by Association for Computing Machinery
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White Papers
Application-Aware NoC Design for Efficient SDRAM Access
Jun 2010
In many-core processors based on Networks-on-Chip (NoC), memory Quality-of-Service (QoS) becomes one of the most important issues since both memory and on-chip network are critical shared...
Provided by Association for Computing Machinery
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White Papers
An SDRAM-Aware Router for Networks-on-Chip
Jul 2009
This paper presents a NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilization and reduce memory...
Provided by Association for Computing Machinery
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White Papers
Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup
Jan 2008
Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of today's high-end...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM
Oct 2008
In this paper, the authors present a deep subthreshold 6-T SRAM, which was fabricated in an industrial 0.13 m CMOS technology. The authors first use detailed simulations to explore the challenges...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A 5.42nW/kB Retention Power Logic-Compatible Embedded DRAM With 2T Dual-Vt Gain Cell for Low Power Sensing Applications
Jan 2011
A logic-compatible 2T dual-Vt embedded DRAM (eDRAM) is proposed for ultra-small sensing systems to achieve 8× longer retention time, 5× lower refresh power and 30% reduced area compared with the...
Provided by University of Michigan
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White Papers
SSA - Superblock-Based Storage Architecture: A New Approach for Boosting I/O Performance
Jan 2011
Many of the new I/O architectures like DCD, RAPID cache and LFS focus on improving the disk write performance. However, many I/O intensive applications are read-dominated or generate substantial...
Provided by University of Cincinnati
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White Papers
Floating Codes for Joint Information Storage in Write Asymmetric Memories
Apr 2007
Memories whose storage cells transit irreversibly between states have been common since the beginning of the data storage technology. Examples include punch cards and digital optical discs, where...
Provided by Texas A&M University
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White Papers
Joint Coding for Flash Memory Storage
Apr 2008
Flash memory is an electronic non-volatile memory with wide applications. Due to the substantial impact of block erasure operations on the speed, reliability and longevity of flash memories,...
Provided by Texas A&M University
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White Papers
On the Capacity of Bounded Rank Modulation for Flash Memories
Jun 2009
Rank modulation has been recently introduced as a new information representation scheme for flash memories. Given the charge levels of a group of flash cells, sorting is used to induce a...
Provided by California Institute of Technology
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White Papers
Storage Coding For Wear Leveling in Flash Memories
Feb 2009
NAND flash memories are currently the most widely used type of flash memories. In a NAND flash memory, although a cell block consists of many pages, to rewrite one page, the whole block needs to...
Provided by Texas A&M University
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White Papers
Universal Rewriting in Constrained Memories
Apr 2009
A constrained memory is a storage device whose elements change their states under some constraints. A typical example is flash memories, in which cell levels are easy to increase but hard to...
Provided by Texas A&M University
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White Papers
Data Movement and Aggregation in Flash Memories
Jan 2010
NAND flash memories have become the most widely used type of non-volatile memories. In a NAND flash memory, every block of memory cells consists of numerous pages, and rewriting a single page...
Provided by Texas A&M University
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White Papers
Fit a Spread Estimator in Small Memory
May 2009
The spread of a source host is the number of distinct destinations that it has sent packets to during a measurement period. A spread estimator is a software/hardware module on a router that...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
The Design and Implementation of RAPID-Cache: A Reliable, Inexpensive, and High-Performance I/O Cache for Linux
Jan 2011
Most file system performance enhancing techniques, such as the I/O buffer cache and the Log-structured File Systems (LFS), relying on caching data in volatile RAM for a period of time before...
Provided by University of Cincinnati
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White Papers
Wireless Sensor Networks for Healthcare
May 2010
Driven by the confluence between the need to collect data about people's physical, physiological, psychological, cognitive, and behavioral processes in spaces ranging from personal to urban and...
Provided by Harvard University
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Case Studies
Fortune 500 Outsourcing Service Provider Satisfies Customer Demands for Fast Access to Document Images with Active Archiving Solution
Sep 2006
"We can retrieve an archive in 40 seconds. This is a crucial capability, enabling us to meet service-level agreements. Our clients must get real-time visibility into their expenditures to do...
Provided by PowerFile
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White Papers
The Evolution of the Electronics Industry
May 2012
Transistor by transistor, the electronics industry is literally changing the world. Consider the following: today's fastest computers can now achieve 10 quadrillion operations a second1; by 2015,...
Provided by IBM
-
White Papers
Design and VLSI Implementation of DDR SDRAM Controller for High Speed Applications
Jul 2011
Synchronous DRAM (SDRAM) has become a mainstream memory of choice in design due to its speed, burst access and pipeline features. For high-end applications using processors, the interface to the...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
Method to Minimize the Clock Skew and Uniform Clock Distribution Using Parallel Port in Pipe Line Based Multi Channel DMA Request Terminal for Frequency Measurement
Jun 2010
This paper presents a new wide-range digital speed measurement method with jitter removal technique and using the Direct Memory Access (DMA) Terminal Count Register (TCR). The authors' work also...
Provided by International Journal of Computer Science and Information Technologies
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White Papers
Design and FPGA Implementation of DDR3 SDRAM Controller for High Performance
Aug 2011
The demand for faster and cheaper memories has been increasing by the day. Hence, these memory devices are rapidly developing to give high density and high memory bandwidths. However, with the...
Provided by Academy & Industry Research Collaboration Center
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White Papers
Using Subthreshold SRAM to Design Low-Power Crypto Hardware
Aug 2011
Cryptography and Security hardware architecture designing is in essential need for efficient power utilization which is achieved earlier by giving a range of tradeoff between speed and power...
Provided by Umm Al-Qura University
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White Papers
To Reduce SRAM Sub-Threshold Leakage Using Stack and Zig-Zag Techniques
Apr 2012
The growing market of portable electronics devices demands lesser power dissipation for longer battery life and compact system. Considerable attention has been given to the design of low-power and...
Provided by International Journal of Scientific Engineering and Technology
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White Papers
Deep Sub-Micron SRAM Design for DRV Analysis and Low Leakage
Nov 2011
This paper deals with the design opportunities of Static Random Access Memory (SRAM) for lower power consumption and propagation delay. Initially, the existing SRAM architectures are investigated,...
Provided by International Journal of Advances in Engineering & Technology (IJAET)
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White Papers
Analysis of Leakage Reduction Technique on Different SRAM Cells
Jan 2012
Leakage components is very important for estimation and reduction of leakage power, especially for low power applications. This provides the motivation to explore the design of low leakage SRAM...
Provided by International Journal of Engineering Trends and Technology
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White Papers
Predator: A Predictable SDRAM Memory Controller
Oct 2007
Memory requirements of Intellectual Property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAMs, are shared...
Provided by Association for Computing Machinery
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White Papers
Improved Power Modeling of DDR SDRAMs
Jun 2011
Power modeling and estimation has become one of the most defining aspects in designing modern embedded systems. In this context, DDR SDRAM memories contribute significantly to system power...
Provided by Delft University of Technology
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White Papers
Automatic Generation of Efficient Predictable Memory Patterns
Jun 2011
Verifying firm real-time requirements get increasingly complex, as the number of applications in embedded systems grows. Predictable systems reduce the complexity by enabling formal verification....
Provided by Eindhoven University of Technology (TU/e)
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White Papers
Memory Controllers for High-Performance and Real-Time MPSoCs
Oct 2011
3D stacking of multi-core heterogeneous system opens a new era of architecture exploration with new partitioning of the overall System-on-Chip. After a description of the 3D stacking technologies,...
Provided by Association for Computing Machinery
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White Papers
Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations
Oct 2008
This paper examines the hardware implementation trade-offs when evaluating functions via piecewise polynomial approximations and interpolations for precisions of up to 24 bits. In polynomial...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method
Aug 2007
The authors have presented an automated methodology for producing hardware-based non-uniform RNG designs using the inversion method. The designs are capable of generating random numbers from...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Rate-Based Pacing for Optical Packet Switched Networks With Very Small Optical RAM
Aug 2007
The authors show that by applying rate-based pacing at the edge nodes, very small optical RAM buffers can be enough for high utilization and low packet drop ratio inside core Optical...
Provided by Osaka University
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White Papers
Simple But Effective Heterogeneous Main Memory With On-Chip Memory Controller Support
Nov 2010
System-in-Package (SiP) and 3D integration are promising technologies to bring more memory onto a microprocessor package to mitigate the "Memory wall" problem. In this paper, instead of using them...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes
Jul 2006
Efficient soft-decision decoding of Reed - Solomon (RS) codes is made possible by the Koetter - Vardy (KV) algorithm which consists of a front-end to the interpolation-based Guruswami - Sudan (GS)...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Design and Modelling of Paralleled RAM Architecture
Jan 2012
In this paper a structural approach to the design of Two-Dimensional (2D) addressing mode Static Random Access Memory (RAM) using Very High Speed Integrated Circuit Hardware Description Language...
Provided by International Association of Computer Science & Information Technology (IACSIT)
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White Papers
Re-Architecting DRAM Memory Systems With Monolithically Integrated Silicon Photonics
Jun 2010
The performance of future many-core processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of electrical DRAM...
Provided by Association for Computing Machinery
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White Papers
Sparse Indexing: Large Scale, Inline Deduplication Using Sampling and Locality
Jan 2009
The authors present sparse indexing, a technique that uses sampling and exploits the inherent locality within backup streams to solve for large-scale backup (e.g., hundreds of terabytes) the...
Provided by University of California
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White Papers
Handheld System Energy Reduction by OS-Driven Refresh
Dec 2009
Emerging portable devices relay on DRAM/flash memory system to satisfy requirements on fast and large data storage and low-energy consumption. This paper presents a novel approach to reduce energy...
Provided by Springer Science+Business Media
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White Papers
Reducing Energy of DRAM/Flash Memory System by OS-Controlled Data Refresh
Jun 2007
This paper presents a new approach to reduce energy consumption of DRAM/flash memory system by lowering the frequency of DRAM refreshes. The approach is based on two ideas: a DRAM based swap-cache...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Hardware Efficient Approach for Memoryless-Based Multiplication and Its Application to FIR Filter
Nov 2011
In conventional memory-based multiplication design, the multiplier is replaced by a read only memory (ROM). Since the memory size increases exponentially with the input length, in this paper, a...
Provided by Academy Publisher
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White Papers
An Approach for Adaptive DRAM Temperature and Power Management
Jun 2008
With rising capacities and higher accessing frequencies, high-performance DRAMs are providing increasing memory access bandwidth to the processors. However, the increasing DRAM performance comes...
Provided by Association for Computing Machinery
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White Papers
Hardware/Software Techniques for DRAM Thermal Management
Dec 2010
The performance of the main memory is an important factor on overall system performance. To improve DRAM performance, designers have been increasing chip densities and the number of memory...
Provided by Northwestern University
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White Papers
Multijunction Fault-Tolerance Architecture for Nanoscale Crossbar Memories
Mar 2008
Nanoscale elements are fabricated using bottom-up processes, and as such are prone to high levels of defects. Therefore, fault-tolerance is crucial for the realization of practical nanoscale...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
Two-Tier Bloom Filter to Achieve Faster Membership Testing
Mar 2008
Bloom filters are widely used with many applications in the domain of networks. One application of interest is representing large file lists; for example lists of shared files in servers or caches...
Provided by University of South Florida
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White Papers
Application of Nanojunction-Based RRAM to Reconfigurable IC
Aug 2008
In this paper, a novel reconfigurable architecture, rFPGA, is developed by utilizing high-density resistive memory (RRAM) circuits as FPGA components. Different from the existing CMOS-nano hybrid...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
PRML Detection of Multi-Level DVD Channels With Run-Length-Limited Modulation
Jun 2007
Multi-level optical recording using Run-Length-Limited (RLL) modulation is a novel method to significantly increase the information recording density without changing optical or mechanical...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A Software Approach to Unifying Multicore Caches
Jun 2011
Multicore chips will have large amounts of fast on-chip cache memory, along with relatively slow DRAM interfaces. The on-chip cache memory, however, will be fragmented and spread over the chip;...
Provided by Massachusetts Institute of Technology
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Webcasts
Webcast: Ubuntu Cloud
Nov 2011
After years of development and fine tuning, the cloud vision of true computing elasticity is finally a reality. The question now is how organizations can best take advantage of the latest cloud...
Provided by Canonical Ltd
-
White Papers
A DRAM Centric NoC Architecture and Topology Design Approach
Apr 2011
Most communication traffic in today's System on Chips (SoC) is DRAM centric. The NoC should be designed to efficiently handle the many-to-one communication pattern, funneling to and from the DRAM...
Provided by University of Bologna
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White Papers
Design and Implementation of the Honey-DVD
Jun 2006
Honeynets are a valuable source of data about techniques, tactics and motives of attackers in the Internet, but up to now they have been notoriously difficult to set up and maintain. This paper...
Provided by University of Mannheim
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White Papers
Top 10 questions about Ubuntu Server Edition
Jul 2011
What's different about Ubuntu Server? Is it secure enough to use in my business? Will it work on my hardware? Whether you've already deployed Ubuntu in your business or are just starting to...
Provided by Canonical Ltd
-
White Papers
On Avoiding Spare Aborts in Transactional Memory
Aug 2009
This paper takes a step toward developing a theory for understanding aborts in Transactional Memory systems (TMs). Existing TMs may abort many transactions that could, in fact, commit without...
Provided by Association for Computing Machinery
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White Papers
SMV: Selective Multi-Versioning STM
Mar 2010
The authors present Selective Multi-Versioning (SMV), a new STM that reduces the number of aborts, especially those of long read-only transactions. SMV keeps old object versions as long as they...
Provided by Technion - Israel Institute of Technology
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White Papers
Data Remanence in Microcontrollers
Apr 2007
Data remanence affects several memory types that are used in smartcards and microcontrollers. As a result, some information still can be extracted from memory that has been erased. This could...
Provided by University of Twente
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White Papers
Run-Time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration
Jun 2009
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, the authors propose to use Direct Memory Access (DMA),...
Provided by KTH - Royal Institute of Technology
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White Papers
Delay and Energy Consumption Analysis of Conventional SRAM
May 2010
The energy consumption and delay in read/write operation of conventional SRAM is investigated analytically as well as by simulation. Explicit analytical expressions for the energy consumption and...
Provided by Islamic Azad University
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White Papers
DRAM Errors in the Wild: A Large-Scale Field Study
Jun 2009
Errors in Dynamic Random Access Memory (DRAM) are a common form of hardware failure in modern compute clusters. Failures are costly both in terms of hardware replacement costs and service...
Provided by Association for Computing Machinery
-
White Papers
Top 10 questions about Ubuntu Server Edition
Jul 2011
What's different about Ubuntu Server? Is it secure enough to use in my business? Will it work on my hardware? Whether you've already deployed Ubuntu in your business or are just starting to...
Provided by Canonical Ltd
-
Case Studies
Advanced Micro Devices Case Study: Bentley Systems Software
Jan 2009
With over 2,800 colleagues in over 50 offices worldwide and annual revenues surpassing $450 million, Bentley Systems has invested over $I billion in research, development and acquisitions since...
Provided by Advanced Micro Devices (AMD)
-
White Papers
Incident Response: Speed Can Mean the Difference Between Success and Failure
Nov 2009
When it comes to investigations and incident response speed is all important. The faster an examiner gets the data in a consumable form the faster an incident can be diagnosed and resolved. Even...
Provided by AccessData
-
White Papers
Redundant Optical Storage System Using DVD-RAM Library
May 2009
A Digital Virtual Disk (DVD) Random Access Memory (RAM) Redundant Array of Inexpensive Libraries (RAIL) optical storage system has been developed and tested at NTT Integrated Information & Energy...
Provided by NTT Communication Science Laboratories
-
White Papers
The Value of Using ECC Memory in Embedded Applications
Oct 2009
This paper provides an introduction to Error Correcting Code (ECC) DRAM. It discusses the risks of a system encountering random memory errors and the approaches for combating them. DRAM is...
Provided by Advanced Micro Devices
-
White Papers
Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces
Nov 2007
The DDR3 SDRAM memory architectures support higher bandwidths with bus rates of 600 Mbps to 1.6 Gbps (300 to 800 MHz), 1.5V operation for lower power, and higher densities of 2 Gbits on a 90-nm...
Provided by Altera
-
White Papers
CA-RAM: A High-PerformanceMemory Substrate for Search-Intensive Applications
Feb 2007
This paper proposes a specialized memory structure called CA-RAM (Content Addressable Random Access Memory) to accelerate search operations present in many important real-world applications....
Provided by University of Pittsburgh
-
White Papers
Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance
Dec 2009
The Phase-Change Random Access Memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmability, low-power...
Provided by Association for Computing Machinery
-
White Papers
Storage-Class Memory: The Next Storage System Technology
Sep 2008
Maintaining the performance growth rate of the 30-yearold system memory and storage hierarchy, primarily based on DRAM (Dynamic RAM) and disks, has become a major challenge in the design of...
Provided by IBM
-
White Papers
Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores
Jun 2010
DRAM vendors have traditionally optimized the cost-per-bit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, where a single...
Provided by Association for Computing Machinery
-
White Papers
Micro-Pages: Increasing DRAM Efficiency With Locality-Aware Data Placement
Mar 2010
Power consumption and DRAM latencies are serious concerns in modern Chip-MultiProcessor (CMP or Multi-core) based compute systems. The management of the DRAM row buffer can significantly impact...
Provided by Association for Computing Machinery
-
White Papers
Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM
Jun 2006
Measurements of an off-the-shelf DRAM chip confirm that different cells retain information for different amounts of time. This result extends to DRAM rows, or pages (Retention time of a page is...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation With Application to SRAM Circuit Design
Jul 2007
Circuit reliability under statistical process variation is an area of growing concern. For highly replicated circuits such as SRAMs and flip flops, a rare statistical event for one circuit may...
Provided by Carnegie Mellon University
-
White Papers
Extended Abstract: The Butterfly PUF Protecting IP on Every FPGA
Jul 2008
IP protection of hardware designs is the most important requirement for many FPGA IP vendors. To this end, various solutions have been proposed by FPGA manufacturers based on the idea of bitstream...
Provided by Katholieke Universiteit Leuven
-
White Papers
Suitability of Requirements Abstraction Model (RAM) Requirements for High-Level System Testing
Jun 2009
The Requirements Abstraction Model (RAM) helps in managing abstraction in requirements by organizing them at four levels (product, feature, function and component). The RAM is adaptable and can be...
Provided by Katholieke Universiteit Leuven
-
White Papers
3D Network-on-Chip With On-Chip DRAM: An Empirical Analysis for Future Chip Multiprocessor
Nov 2010
With the increasing number of on-chip components and the critical requirement for processing power, Chip MultiProcessor (CMP) has gained wide acceptance in both academia and industry during the...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
A Low Power SRAM Base on Novel Word-Line Decoding
Jun 2009
This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to...
Provided by Islamic Azad University
-
White Papers
Fundamental Redundancy Versus Power Trade-Off in Standby SRAM
Jan 2007
The authors study the problem of reducing power during data-retention in a standby Static Random Access Memory (SRAM). For successful data-retention, the supply voltage of an SRAM cell should be...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
Nov 2008
Intermittently-powered applications create a need for low-cost security and privacy in potentially hostile environments, supported by primitives including identification and random number...
Provided by Institute of Electrical and Electronics Engineers
-
White Papers
Design and Implementation of 8K-Bits Low Power SRAM in 180nm Technology
Mar 2009
This paper explores the tradeoffs that are involved in the design of SRAM. The major components of an SRAM such as the row decoders, the memory cells and the sense amplifiers have been studied in...
Provided by SV College of Engineering & Technology
-
White Papers
Online Memory Compression for Embedded Systems
Feb 2010
Memory is a scarce resource during embedded system design. Increasing memory often increases packaging costs, cooling costs, size, and power consumption. This paper presents CRAMES, a novel and...
Provided by Association for Computing Machinery
-
White Papers
MEMMU: Memory Expansion for MMU-Less Embedded Systems
Apr 2009
Random Access Memory (RAM) is tightly constrained in the least expensive, lowest-power embedded systems such as sensor network nodes and portable consumer electronics. The most widely used sensor...
Provided by Association for Computing Machinery
-
White Papers
Application-Aware NoC Design for Efficient SDRAM Access
Jun 2010
In many-core processors based on Networks-on-Chip (NoC), memory Quality-of-Service (QoS) becomes one of the most important issues since both memory and on-chip network are critical shared...
Provided by Association for Computing Machinery
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White Papers
An SDRAM-Aware Router for Networks-on-Chip
Jul 2009
This paper presents a NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilization and reduce memory...
Provided by Association for Computing Machinery
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White Papers
Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup
Jan 2008
Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of today's high-end...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM
Oct 2008
In this paper, the authors present a deep subthreshold 6-T SRAM, which was fabricated in an industrial 0.13 m CMOS technology. The authors first use detailed simulations to explore the challenges...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
A 5.42nW/kB Retention Power Logic-Compatible Embedded DRAM With 2T Dual-Vt Gain Cell for Low Power Sensing Applications
Jan 2011
A logic-compatible 2T dual-Vt embedded DRAM (eDRAM) is proposed for ultra-small sensing systems to achieve 8× longer retention time, 5× lower refresh power and 30% reduced area compared with the...
Provided by University of Michigan
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White Papers
SSA - Superblock-Based Storage Architecture: A New Approach for Boosting I/O Performance
Jan 2011
Many of the new I/O architectures like DCD, RAPID cache and LFS focus on improving the disk write performance. However, many I/O intensive applications are read-dominated or generate substantial...
Provided by University of Cincinnati
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White Papers
Floating Codes for Joint Information Storage in Write Asymmetric Memories
Apr 2007
Memories whose storage cells transit irreversibly between states have been common since the beginning of the data storage technology. Examples include punch cards and digital optical discs, where...
Provided by Texas A&M University
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White Papers
Joint Coding for Flash Memory Storage
Apr 2008
Flash memory is an electronic non-volatile memory with wide applications. Due to the substantial impact of block erasure operations on the speed, reliability and longevity of flash memories,...
Provided by Texas A&M University
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White Papers
On the Capacity of Bounded Rank Modulation for Flash Memories
Jun 2009
Rank modulation has been recently introduced as a new information representation scheme for flash memories. Given the charge levels of a group of flash cells, sorting is used to induce a...
Provided by California Institute of Technology
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White Papers
Storage Coding For Wear Leveling in Flash Memories
Feb 2009
NAND flash memories are currently the most widely used type of flash memories. In a NAND flash memory, although a cell block consists of many pages, to rewrite one page, the whole block needs to...
Provided by Texas A&M University
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White Papers
Universal Rewriting in Constrained Memories
Apr 2009
A constrained memory is a storage device whose elements change their states under some constraints. A typical example is flash memories, in which cell levels are easy to increase but hard to...
Provided by Texas A&M University
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White Papers
Data Movement and Aggregation in Flash Memories
Jan 2010
NAND flash memories have become the most widely used type of non-volatile memories. In a NAND flash memory, every block of memory cells consists of numerous pages, and rewriting a single page...
Provided by Texas A&M University
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White Papers
Fit a Spread Estimator in Small Memory
May 2009
The spread of a source host is the number of distinct destinations that it has sent packets to during a measurement period. A spread estimator is a software/hardware module on a router that...
Provided by Institute of Electrical and Electronics Engineers
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White Papers
The Design and Implementation of RAPID-Cache: A Reliable, Inexpensive, and High-Performance I/O Cache for Linux
Jan 2011
Most file system performance enhancing techniques, such as the I/O buffer cache and the Log-structured File Systems (LFS), relying on caching data in volatile RAM for a period of time before...
Provided by University of Cincinnati
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White Papers
Wireless Sensor Networks for Healthcare
May 2010
Driven by the confluence between the need to collect data about people's physical, physiological, psychological, cognitive, and behavioral processes in spaces ranging from personal to urban and...
Provided by Harvard University
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Case Studies
Fortune 500 Outsourcing Service Provider Satisfies Customer Demands for Fast Access to Document Images with Active Archiving Solution
Sep 2006
"We can retrieve an archive in 40 seconds. This is a crucial capability, enabling us to meet service-level agreements. Our clients must get real-time visibility into their expenditures to do...
Provided by PowerFile
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White Papers
Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches
Dec 2010
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory technology that is a potential universal memory that could replace SRAM in processor caches. This paper presents a novel...
Provided by University of Virginia
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White Papers
Microsearch: When Search Engines Meet Small Devices
Feb 2008
With the increasing popularity of RFID applications, different authentication schemes have been proposed to provide security and privacy protection to users. Most recent RFID protocols use a...
Provided by College of William and Mary
