Stream Image Processing on a Dual-Core Embedded System

Effective memory utilization is critical to reap the benefits of the multi-core processors emerging on embedded systems. In this paper the authors explore the use of a stream model to effectively utilize memory hierarchies. They target image processing algorithms running on the Analog Devices Blackfin BF561 fixed-point, dual-core DSP. Using optimized assembly to effectively use cores reduces runtime, but also underscores the need to mitigate the memory bottleneck. Like other embedded processors, the Blackfin BF561 has L2 SRAM available. Applying the stream model allows one to effectively make full use of both cores and the L2 SRAM. They achieve almost a 10X speedup in execution time compared to non-optimized C code.