Supporting Unknown FREF Video Applications With PLLs
Cyclone III Phase-Locked Loops (PLLs) are feature rich, supporting advanced capabilities such as clock switchover, dynamic phase shifting, and PLL reconfiguration. Previously, PLLs in Altera Cyclone FPGAs were designed to be configured for a specific input frequency. The newly added Voltage-Controlled Oscillator (VCO) range detector in Cyclone III PLLs, together with the dynamic phase reconfiguration and PLL reconfiguration, enable the support for advanced display applications where the PLL input frequency may not be known ahead of time or may change. In this "unknown FREF video application," the initial input frequency to the PLL is 60 MHz to 80 MHz, varying from 15 MHz to135 MHz in later stages.