System-Level Modeling of a Network-on-Chip

This paper presents the system-level modeling and simulation of a concurrent architecture for a customizable and scalable Network-on-Chip (NoC), using system level tools (Mission Level Designer (MLD)). MLD supports the integration of heterogeneous models of computation, which provide a framework to model various algorithms and activities, while accounting for and exploiting concurrency and synchronization aspects. The methodology consists of three main phases: system-level concurrency modeling, component-level modeling, and system-level integration. The Finite State Processes (FSP) symbolic language is used to model and analyze the system-level concurrency aspects of the NoC.