Temperature-Aware Test Scheduling for Multiprocessor Systems-On-Chip
Source: Northwestern University
Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high Integrated Circuit (IC) temperatures. This has the potential to damage ICs and cause good ICs to be discarded due to temperature-induced timing faults. The authors studied the power impact of scan chain testing for the ISCAS89 benchmarks. They find that the scan-chain test power consumption is 1.6 higher for at-speed testing than normal operating power consumption. They concluded that if the testing frequency is less than half of the normal frequency, then the testing power consumption may in fact be lower. However, due to differences in the cooling environments, the peak die temperatures may still be higher.