The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded Floating Point Units (FPUs) and the fine-grained logic fabric in FPGAs. It also studies this interface in FPGAs which contain both FPUs and embedded memories. The results show that FPUs should have a square aspect ratio; they should be positioned near the center of the FPGA; their I/O pins should be arranged around all four sides of the FPU; embedded memory should be located between the FPUs; and connecting higher I/O density coarse-grained blocks increases the demand for routing resources.